Bus Operation; Bus Status Definitions - Intel 386 User Manual

6.2

BUS OPERATION

The processor generates eight different types of bus operations:
•
Memory data read (data fetch)
•
Memory data write
•
Memory code read (instruction fetch)
•
I/O data read (data fetch)
•
I/O data write
•
Halt or shutdown
•
Refresh
•
Interrupt acknowledge
These operations are defined by the states of four bus status pins: M/IO#, D/C#, W/R# and RE-
FRESH#. Table 6-2 lists the various combinations and their definitions.
M/IO# D/C#
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
1 1
*The byte address is 2 for a halt and 0 for a shutdown. For both conditions, BHE# is high and BLE# is low.
Table 6-2. Bus Status Definitions
W/R# REFRESH#
0 1
1 1
0 1
1 1
0 1
1 1
0 0
0 1
1 1
BUS INTERFACE UNIT
Bus Operation
interrupt acknowledge cycle
never occurs
I/O data read
I/O data write
memory code read
halt or shutdown cycle*
refresh cycle
memory data read
memory data write
6-5