Halt Cycle - Intel 386 User Manual

CLK2
CLKOUT
BHE#, A1, M/IO#, W/R#
A25:2, BLE#, D/C#
WR#
RD#
ADS#
NA#
READY#
LBA#
LOCK#
D15:0
HALT cycle must be acknowledged by READY# asserted. This READY# could be
†
generated internally or externally.
Cycle 1 Cycle 2
Nonpipelined Nonpipelined
(Write) (Halt)
[Late Ready]
T1 T2 T1 T2
Valid 1
Valid 1
Valid 1 Valid 2
Undefined
Out
Figure 6-10. Halt Cycle
BUS INTERFACE UNIT
Idle
Ti Ti Ti Ti
CPU remains halted until INTR, SMI#,
NMI, or RESET is asserted.
CPU responds to HOLD input
while in the HALT state.
†
Float
A2492-02
6-27