Buffer Transfer Ended By An Expired Byte Count; Buffer Transfer Ended By The Eop# Input - Intel 386 User Manual

DMA CONTROLLER
Terminating a buffer transfer by deasserting DREQn can also be done either synchronously or
asynchronously. The effect is identical to that of synchronous or asynchronous sampling of
EOP#. When DREQn is used to terminate a DMA transfer in asynchronous mode, DREQn must
be sampled inactive one CLKOUT before READY#. In synchronous mode it must be sampled
inactive at the same time as READY#. When DREQn is sampled active in either of the above
cases another DMA cycle is executed (depending on operating mode).
T2 T1 T2 Ti T x T x T x
CLKOUT
DRQ n
ADS#
EOP#
(As an output)
READY#
x Cycle
DMA Cycle
A2483-02
Figure 12-6. Buffer Transfer Ended by an Expired Byte Count
T2 T1 T2 T2 T2 T2
Ti
CLKOUT
ADS#
READY#
EOP# (Async)
EOP# (Sync)
DMA Cycle
A2482-02
Figure 12-7. Buffer Transfer Ended by the EOP# Input
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