Timing Information; Internal And External Timing For Loading The Instruction Register - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL

18.4 TIMING INFORMATION

The test-logic unit's input/output timing is as specified in IEEE 1149.1. Figure 18-5 shows the
pin timing associated with loading the instruction register and Figure 18-6 shows the timing for
loading a given data register.
TCK
TMS
Controller State
TDI
Data Input to IR
IR Shift-Register
Parallel Output of IR
Data Input to TDR
TDR Shift-Register
Parallel Output of TDR
Register Selected
TDO Enable
TDO
Figure 18-5. Internal and External Timing for Loading the Instruction Register
18-12
IDCode
Inactive Active
= Don't care or undefined.
Instruction Register
Inactive Active
New Instruction
Old Data
Inactive
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