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Intel F-Tile SDI II Agilex User Manual

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F-Tile SDI II Intel
Agilex
FPGA IP
Design Example User Guide
®
®
Updated for Intel
Quartus
Prime Design Suite: 21.4
IP Version: 19.2.0
ID:
710496
Online Version
Send Feedback
Version:
2022.01.28

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Summary of Contents for Intel F-Tile SDI II Intel Agilex

  • Page 1 ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide ® ® Updated for Intel Quartus Prime Design Suite: 21.4 IP Version: 19.2.0 710496 Online Version Send Feedback Version: 2022.01.28...

  • Page 2: Table Of Contents

    2.4. Simulation......................27 2.4.1. Testbench Components................27 2.4.2. Test Description..................28 2.4.3. Hardware Testing..................29 2.4.4. Signal....................30 3. Document Revision History for the F-Tile SDI II Intel Agilex Design Example User Guide........................39 ® ™ F-Tile SDI II Intel...

  • Page 3: F-Tile Sdi Ii Intel ® Agilex ™ Fpga Ip Design Example Quick Start Guide

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
  • Page 4 ® ™ 1. F-Tile SDI II Intel Agilex FPGA IP Design Example Quick Start Guide 710496 | 2022.01.28 Figure 2. Directory Structure for the Design Examples <Design Example> hwtest simulation quartus generation.log (for serial loopback design) sdi_ii_agi_demo.sv mentor tpg.ctrl.tcl sdi_ii_agi_demo.sdc synopsys sdi_ii_agi_demo.qpf...
  • Page 5 ® ™ 1. F-Tile SDI II Intel Agilex FPGA IP Design Example Quick Start Guide 710496 | 2022.01.28 Folders Files <qsys generated folder> /tx_<vid_std>_top.sv /sdi_<vid_std>_tx_sys.qsys <qsys generated folder> phy_adapter /sdi_ftile_phy_adapter.sv /sdi_ftile_phy_adapter.sdc /rxdata_dcfifo.ip (optional) /rxdata_mwfifo.ip [Only in 12-SDI single rate mode Design Example] txdata_fifo.ip...

  • Page 6: Generating The Design

    1. Create an empty project targeting Intel Agilex device family and select the desired device. 2. In the IP Catalog, locate and double-click SDI II Intel FPGA IP. The IP Parameter Editor window appears. 3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip...

  • Page 7: Simulating The Design

    To run example design simulation, follow these steps: 1. Generate the necessary simulation setup files. a. Using GUI method: Open the Intel Quartus Prime Project in Intel Quartus Prime directory. Run Support-Logic Generation to generate the transceiver RTL files. Figure 6.
  • Page 8 ® ™ 1. F-Tile SDI II Intel Agilex FPGA IP Design Example Quick Start Guide 710496 | 2022.01.28 iii. To generate the simulation setup files, click Tools Generate Simulator Setup Script for IP..iv. Set the output directory to .../simulation Figure 7.

  • Page 9: Compiling And Testing The Design In Hardware

    1. Open the Intel Quartus Prime project ( ) located in sdi_ii_agi_demo.qpf Quartus directory. 2. To perform Intel Quartus Prime compilation, click Processing Start Compilation. 3. Connects the Nextera SDI daughter card to FMC port A on the development kit.
  • Page 10 ® ™ 1. F-Tile SDI II Intel Agilex FPGA IP Design Example Quick Start Guide 710496 | 2022.01.28 Figure 9. Selecting Video Format Through System Console 8. The analyzer should be able to display the video generated from the source. Refer...

  • Page 11: Design Example Parameters

    This option is greyed out and set to always Enabled. This is because synthesis files are still required to run Support- Logic Generation stage in Intel Quartus Prime to generate the transceiver tile’s files which are essential to run simulation as well.
  • Page 12 • Custom Development Kit: This option allows the design example to be tested on a third-party development kit with Intel FPGA device. You may need to set the pin assignment on your own. Change Target Device On / Off Turn on this option and select the preferred device variant for the development kit.

  • Page 13: Design Example Detailed Description

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 14: Hardware And Software Requirements

    2. Design Example Detailed Description 710496 | 2022.01.28 Figure 11. Components required for TX or RX only design on Intel Agilex Device SDI TX Sys SDI RX Sys F-tile PMA/ F-tile PMA/ Video Pattern FEC Direct FEC Direct SDI II...

  • Page 15: Functional Description

    Agilex F-Tile FPGA IP design example fail to compile at the Support-Logic Generation stage? 2.3. Functional Description The SDI II Intel FPGA IP core design example supports the following simplex and duplex transceiver mode:. • Parallel loopback with simplex mode •...
  • Page 16 PLL Clocks IP Parallel Data Control/Status Serial Data Note: Refer to Clocking Scheme on page 22 for the Reference and System PLL Clocks IP connections. ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 17 PLL Clocks IP Parallel Data Control/Status Serial Data Note: Refer to Clocking Scheme on page 22 for the Reference and System PLL Clocks IP connections. ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 18 PLL Clocks IP Parallel Data Control/Status Avalon-MM Serial Data Note: Refer to Clocking Scheme on page 22 for the Reference and System PLL Clocks IP connections. ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...

  • Page 19: Design Components

    Refer to Clocking Scheme on page 22 for the Reference and System PLL Clocks IP connections. 2.3.1. Design Components The SDI II Intel FPGA IP core design examples require the following components. ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide...
  • Page 20 F-tile PMA/FEC Direct PHY IP. System PLL clock output is always set to run at a higher clock frequency than the native PMA recovered clock. continued... ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 21 The module also includes a reset delay block to further delay the signal status from the IP for a safer operation. For more information, refer to Intel Agilex Reset Release Intel FPGA IP in Intel Agilex Configuration User Guide.

  • Page 22: Clocking Scheme

    RX CDR Refclock RX Coreclock/DR Clocks System PLL Refclock TX PLL/RX CDR Link Clock System PLL Output Link Clock TX/RX Transceiver Clkout TX/RX Transceiver Clkout2 ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 23 TX PLL Refclock RX CDR Refclock System PLL Refclock RX Coreclock TX PLL/RX CDR Link Clock System PLL Output Link Clock TX/RX Transceiver Clkout TX/RX Transceiver Clkout2 ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 24 RX CDR Refclock System PLL Refclock RX Coreclock TX PLL/RX CDR Link Clock System PLL Output Link Clock TX/RX Transceiver Clkout TX/RX Transceiver Clkout2 Note: ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 25 Reference and System PLL Clocks IP, before connecting the corresponding output port to SDI top module. continued... ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 26 DCFIFO which is interfacing between SDI II IP and the Direct PHY IP. Note: Intel recommends you not to share TX PLL reference clock with RX transceiver reference clock for a parallel loopback design because TX PLL clock is going to be tuned to match RX recovered clock frequency.

  • Page 27: Simulation

    PLL Clocks IP Parallel Data Control/Status Serial Data Note: Refer to Clocking Scheme on page 22 for the Reference and System PLL Clocks IP connections. ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...

  • Page 28: Test Description

    2.4.2. Test Description The simulation only checks for the assertion of signal and the number of trs_locked transceiver reconfiguration triggered after every video standard switching. ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...

  • Page 29: Hardware Testing

    LEDs are used to display the RX status. • For Agilex I-series SoC Development Kit and more details on LEDs status, refer to Intel Agilex I-Series Development Kit User LEDs Figure and the D3-D5 LED status and its video standard on Agilex I-series SoC Dev Kit Table.

  • Page 30: Signal

    SGPIO slave signals. These groups of signals connect to fpga_sgpio_clk the MAX device to control the on-board LEDs and DIPSW. Input fpga_sgpio_sync Input fpga_sgpi continued... ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 31 RX transceiver recovered parallel clock for video data. rx_vid_clkout Output TX transceiver recovered parallel clock for video data. tx_vid_clkout Reset Input TX core and PHY reset signal. tx_resetn continued... ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 32 • 3’b001: HD-SDI • 3’b011: 3G-SDI Level A 10-bit Multiplex • 3’b010: 3G-SDI Level B 10-bit Multiplex • 3’b101: 6G-SDI 10-bit Multiplex Type 1 continued... ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 33 Received video transport format. Refer to IP User Guide sdi_rx_format for the encoding value. Output Active picture interval timing signal. This signal is sdi_rx_ap asserted when the active picture interval is active continued... ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 34 Indicates that TX transceiver is out of reset and ready for gxb_tx_ready data transfer. Output Indicates that TX transceiver is reset. gxb_tx_reset_ack Output Indicates that RX transceiver is reset. gxb_rx_reset_ack continued... ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 35 TRS to SDI TX core. Output Indicates the desired transmit video standard to SDI TX sdi_tx_std core. Note: N=4 for multi rate, otherwise N=1. ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 36 TRS output signal to be connected to tx_vid_trs input signal on TX/Du top. Output 11*N Line number output signal to be connected to sdi_tx_ln input signal on TX/Du top. continued... ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 37 Output Output control signal from PIO to control video pattern pattgen_ctrl_pio_out generator. _port ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...
  • Page 38 CNTR_BITS Note: parameter determines the bit width of CNTR_BITS the delay counter. Default value is set to 16. ® ™ F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide Send Feedback...

  • Page 39: Document Revision History For The F-Tile Sdi Ii Intel Agilex Design Example User Guide

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

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