Divisor Latch Registers (Dll N And Dlh N ) - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL

11.3.3 Divisor Latch Registers (DLL n and DLH n )

Use these registers to program the baud-rate generator's output frequency. The baud-rate gener-
ator's output determines the transmitter and receiver bit times.
Divisor Latch Low
DLL0, DLL1
(read/write)
7
LD7 LD6
Divisor Latch High
DLH0, DLH1
(read/write)
7
UD15 UD14
Bit Bit
Number Mnemonic
DLL n LD7:0
(7–0)
DLH n
UD15:8
(7–0)
NOTE: The divisor latch registers share address ports with other SIO registers. Bit 7 (DLAB) of
LCR n must be set in order to access the divisor latch registers.
If DLL = DLH = 00H, baud-rate generator ouput frequency = 0 (stops clock).
Figure 11-12. Divisor Latch Registers (DLL n and DLH n )
11-22
LD5 LD4
UD13 UD12
Lower 8 Divisor and Upper 8 Divisor Bits:
Write the lower 8 divisor bits to DLL n and the upper 8 divisor bits to
DLH n . The baud-rate generator output is a function of the baud-rate
generator input (BCLKIN) and the 16-bit divisor.
baud-rate generator output frequency
bit rate (shifting rate) = baud-rate generator output frequency/16
DLL0
Expanded Addr: F4F8H
ISA Addr: 03F8H
Reset State: 02H
LD3 LD2
DLH0
Expanded Addr: F4F9H
ISA Addr: 03F9H
Reset State: 00H
UD11 UD10
Function
BCLKIN frequency
= ---------------------------------------------------- -
DLL1
F8F8H
02F8H
02H
0
LD1 LD0
DLH1
F8F9H
02F9H
00H
0
UD9 UD8
diviso r