Autotransmit Mode; Slave Mode; Receiver - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
13.2.2.2

Autotransmit Mode

Set the AUTOTXM bit (SSIOCON2.2) and the TXMM bit (SSIOCON2.1) to enable Autotrans-
mit mode. When the AUTOTXM bit is set, the word is automatically transferred to the shift reg-
ister and the THBE bit is set. In this mode the TEN bit is ignored. Once the data is transferred to
the shift register, the word is shifted out. If no new data has been written into the buffer, the trans-
mitter stops.
The Transmit Underrun Error (TUE) bit is not used in Autotransmit mode.
The Autotransmit mode eliminates the problem of controlling the TEN bit during high-speed data
transfers using polling or interrupts to move new data to the transmit buffer (SSIOTBUF).
13.2.2.3

Slave Mode

Operation in transmitter slave mode is similar to master mode, except the transmitter is clocked
from the STXCLK pin. When the transmitter is enabled any time during the STXCLK clock cy-
cle, TB15 appears on the SSIOTX pin and remains on the pin until the second falling edge of
STXCLK.

13.2.3 Receiver

The receiver contains a 16-bit holding buffer and a 16-bit shift register. When enabled, the shift
register shifts data in via the SSIORX pin. After the receiver shifts in 16 bits of data, the contents
of the shift register are transferred to the buffer. Either the internal baud-rate generator (master
mode) or an input signal on the SRXCLK pin (slave mode) can clock the receiver.
The receiver contains a receive holding buffer full flag (RHBF) and a receive overflow error flag
(ROE). At reset, RHBF is clear, indicating that the buffer is empty. When the receiver transfers
data from the shift register to the buffer, RHBF is set. Reading the buffer clears RHBF. When the
receiver is enabled, it transfers the contents of the shift register to the receive buffer each time the
shift register finishes shifting its current contents. If the shift register finishes shifting in its cur-
rent contents before the old value is read from the receive buffer, the receiver transfers the new
value into the buffer, overwriting the old value and sets the ROE flag. This condition is known as
a receive overflow error.
The receiver also has an internal receive holding buffer full signal (SSRBF). This signal can be
connected to the DMA unit for DMA initiated transfers. The SSRBF signal is also ORed with the
SSTBE signal to generate the SSIOINT signal which is sent to the interrupt controller. Before the
SSRBF signal is ORed it is masked with the Receive Interrupt Bit (RIE) in the SSIOCON1 reg-
ister. These options allow you to use either an interrupt service routine or a DMA transfer to read
data from the receive holding buffer.
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