Intel 386 User Manual page 473

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
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If the counter value stored in the Refresh Clock Interval Register (RFSCIR) is <8 and the
RCU is enabled, the RCU always has bus control and other devices will never gain access
to the bus. This is because refresh requests have the highest priority in the bus arbitration
scheme and you are requesting the bus too often.
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There are two common methods of refreshing DRAM: RAS#-only and CAS#-before-
RAS#.
— RAS#-only refresh takes advantage of the Intel386 EX Embedded Processor's built in
refresh address counter (RFSADD).
— In a CAS#-before-RAS# refresh, the DRAM provides the row address for the refresh
cycle. The RCU counter still generates the row addresses, but they are disregarded by
the DRAM. The only external logic required is a PLD to recognize a refresh cycle and
provide the CAS# and RAS# signals to the DRAM.
Page Mode
15-12
A paged DRAM access uses the upper address lines for the row
addresses and the lower lines for the column addresses. On the
Intel386 EX embedded processor, the lower address lines are
connected to the Refresh Address Counter Register (RFSADD). The
RFSADD increments through a set sequence at each refresh request.
Because the lower address bits (wired to the Column Address Buffer)
change with each refresh request, the PLD must enable this buffer
when RAS# is asserted during a refresh cycle. Figure 15-7 shows the
external logic needed for paged RAS#-only refresh cycles. The PLD
can determine a refresh cycle by monitoring BHE# and BLE# (they
are both inactive during a refresh cycle), or by an active signal on the
REFRESH# pin. The buffer and lines that are active during this type
of refresh have a shaded background in Figure 15-7.