Rfscir; Rfscon; D.54 Rfscir; D.55 Rfscon - Intel 386 User Manual

D.54 RFSCIR

Refresh Clock Interval

RFSCIR

(read/write)
15
— —
7
RC7 RC6
Bit Bit
Number Mnemonic
15–10 —
9–0 RC9:0

D.55 RFSCON

Refresh Control

RFSCON

(read/write)
15
REN —
7
CV7 CV6
Bit Bit
Number Mnemonic
15 REN
14–10 —
9–0 CV9:0
— —
RC5 RC4
Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
Refresh Counter Value:
Write the counter value to these ten bits. The interval counter counts
down from this value. When the interval counter reaches one, the control
unit initiates a refresh request (provided it does not have a request
pending). The counter value is a function of DRAM specifications and
processor frequency (see the equation above).
— —
CV5 CV4
Refresh Control Unit Enable:
This bit enables or disables the refresh control unit.
0 = Disables refresh control unit
1 = Enables refresh control unit
Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
Counter Value:
These read-only bits represent the current value of the interval counter.
Write operations to these bits have no effect.
SYSTEM REGISTER QUICK REFERENCE
Expanded Addr: F4A2H
ISA Addr: —
Reset State: 0000H
— —
RC3 RC2
Function
Expanded Addr: F4A4H
ISA Addr: —
Reset State: 0000H
— —
CV3 CV2
Function
8
RC9 RC8
0
RC1 RC0
8
CV9 CV8
0
CV1 CV0
D-55