Intel 386 User Manual page 9

Intel386™ EX MICROPROCESSOR USER'S MANUAL
CHAPTER 11
ASYNCHRONOUS SERIAL I/O UNIT
11.1 OVERVIEW ................................................................................................................. 11-1
11.1.1 SIO Signals .............................................................................................................11-3
11.2 SIO OPERATION ........................................................................................................ 11-4
11.2.1 Baud-rate Generator ...............................................................................................11-4
SIO n Transmitter .....................................................................................................11-6
11.2.2
SIO n Receiver .........................................................................................................11-9
11.2.3
11.2.4 Modem Control .....................................................................................................11-12
11.2.5 Diagnostic Mode ...................................................................................................11-12
11.2.6 SIO Interrupt and DMA Sources ...........................................................................11-13
11.2.6.1 SIO Interrupt Sources ......................................................................................11-13
11.2.6.2 SIO DMA sources ............................................................................................11-13
11.2.7 External UART Support ........................................................................................11-14
11.3 REGISTER DEFINITIONS......................................................................................... 11-15
11.3.1 Pin and Port Configuration Registers (PINCFG and P n CFG [ n = 1-3]) ................11-17
11.3.2 SIO and SSIO Configuration Register (SIOCFG) .................................................11-21
11.3.3 Divisor Latch Registers (DLL n and DLH n ) ............................................................11-22
11.3.4 Transmit Buffer Register (TBR n ) ...........................................................................11-23
11.3.5 Receive Buffer Register (RBR n ) ...........................................................................11-24
11.3.6 Serial Line Control Register (LCR n ) ......................................................................11-25
Serial Line Status Register (LSR n ) .......................................................................11-26
11.3.7
Interrupt Enable Register (IER n ) ...........................................................................11-27
11.3.8
Interrupt ID Register (IIR n ) ....................................................................................11-28
11.3.9
11.3.10 Modem Control Register (MCR n ) ..........................................................................11-29
11.3.11 Modem Status Register (MSR n ) ...........................................................................11-31
11.3.12 Scratch Pad Register (SCR n ) ...............................................................................11-32
11.4 PROGRAMMING CONSIDERATIONS...................................................................... 11-32
11.4.1 Asynchronous Serial I/O Unit Code Examples ......................................................11-33
CHAPTER 12
DMA CONTROLLER
12.1 OVERVIEW ................................................................................................................. 12-1
12.1.1 DMA Terminology ...................................................................................................12-3
12.1.2 DMA Signals ...........................................................................................................12-4
12.2 DMA OPERATION....................................................................................................... 12-5
12.2.1 DMA Transfers ........................................................................................................12-5
12.2.2 Bus Cycle Options for Data Transfers .....................................................................12-5
12.2.2.1 Fly-By Mode .......................................................................................................12-5
12.2.2.2 Two-Cycle Mode ................................................................................................12-6
12.2.2.3 Programmable DMA Transfer Direction .............................................................12-6
12.2.2.4 Ready Generation For DMA Cycles ...................................................................12-7
12.2.2.5 DMA Usage of the 4-Byte Temporary Register ..................................................12-7
12.2.3 Starting DMA Transfers ..........................................................................................12-9
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