Paged Dram Interface; Intel386 Ex Processor To Paged Dram Interface - Intel 386 User Manual

6.6.4

Paged DRAM Interface

External logic is required to interface the Intel386 EX processor to DRAM devices, as shown in
Figure 6-18. The PLD generates the RAS# and CAS# signals.
If RAS#-Only Refresh is being performed (using the Refresh Control Unit of the processor), then
during a Refresh Cycle, the PLD enables the Column Address Buffer and asserts the RAS# signal
(shaded sections in the figure). Refer to Chapter 6, "BUS INTERFACE UNIT," for more infor-
mation.
A single multiplexer can be used instead of the separate row and column address buffers.
Upper Address
Intel386™ EX
Embedded Processor
Lower Address
Note:
A single mux can be used in place of the row and column address buffers.
Figure 6-18. Intel386 EX Processor to Paged DRAM Interface
Row
Address
Buffer
OE_ROW#
REFRESH#
BHE#
PLD
CS n #
BLE#
OE_COL#
Column
Address
Buffer
BUS INTERFACE UNIT
Row
Address
Address
RAS#
CAS#
Column
Address
Paged
DRAM
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