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Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU Documentation Update

Intel core 2 extreme quad-core mobile processor, intel core2 quad mobile processor, intel core 2 extreme mobile processor, intel core 2 duo mobile processor, intel core 2 solo mobile processor and intel celeron processor on 45-nm process specification upd
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®
Intel
Core™2 Extreme Quad-Core Mobile
Processor,
®
Intel
Core™2 Quad Mobile Processor,
®
Intel
Core™2 Extreme
®
Intel
Core™2 Duo Mobile Processor,
®
Intel
Core™2 Solo Mobile
®
Intel
Celeron®
on 45-nm Process
Specification Update
December 2011
Mobile Processor,
Processor
Processor and
Document Number: 320121-008

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  Summary of Contents for Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU

  • Page 1 ® Intel Core™2 Extreme Quad-Core Mobile Processor, ® Intel Core™2 Quad Mobile Processor, ® Intel Core™2 Extreme Mobile Processor, ® Intel Core™2 Duo Mobile Processor, ® Intel Core™2 Solo Mobile Processor and ® Intel Celeron® Processor on 45-nm Process Specification Update...
  • Page 2 MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
  • Page 3: Table Of Contents

    Contents Preface ..........................5 Identification Information ......................7 Summary Tables of Changes ....................13 Errata ..........................21 Specification Changes ......................53 Specification Clarifications ..................... 54 Documentation Changes ......................56 Specification Update...
  • Page 4 Revision History Document Revision Version Description Date Number 320121 Initial release July 2008 320121 August 2008  Updated Title  Updated Identification Information  Updated Affected Documents  Added Erratum AZ62, AZ63, AZ64,AZ65, AZ66 320121  Added Erratum AZ66-74 October 2008 320121 ...
  • Page 5: Preface

    Core™2 Quad Processor on 45-nm Process for Platforms based on Mobile Intel® 4 Series Express Chipset family Datasheet Intel® Celeron Processor Low Voltage and Ultra Low Voltage o 700 320389 Series for Platforms based on Mobile Intel® GS45 Express Chipset...
  • Page 6 IA-32 Intel® Architecture Optimization Reference Manual 248966 Intel Processor Identification and the CPUID Instruction Application 241618 Note (AP-485) Intel® 64 and IA-32 Architectures Application Note TLBs, Paging- 317080 Structure Caches, and Their Invalidation NOTE: Contact your Intel representative for the latest revision. Nomenclature Errata are design defects or errors.
  • Page 7: Identification Information

    Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2 Quad Mobile Processor, Intel® Core™2 Extreme Mobile Processor, Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Celeron® Processor on 45- nm Process stepping can be identified by the following register contents:...
  • Page 8 Figure 1. Processor S-Spec Top-side Markings (Example) MARK EXAMPLE: Group 1 Line 1: Unit Identifier Processor # Group 1 Line 2: FPO SSPEC# Group 2 Line 1: Frequency/L2 Cache/FSB Speed Group 2 Line 2: INTEL (m) © ’07 Specification Update...
  • Page 9 Identification Information Table 1. Processor Identification Information Core Frequency Package CPUID HFM/LFM/ SLFM Notes Spec# (GHz) SLAQH T9500 m-FCPGA 000010676h 2.6/1.2/0.8 2,3,4 SLAPW T9500 m-FCBGA 000010676h 2.6/1.2/0.8 2,3,4 SLAQG T9300 m-FCPGA 000010676h 2.5/1.2/0.8 2,3,4 SLAPV T9300 m-FCBGA 000010676h 2.5/1.2/0.8 2,3,4 SLAPU T8300 m-FCBGA...
  • Page 10 Identification Information Core Frequency Package CPUID HFM/LFM/ SLFM Notes Spec# (GHz) SLB4M P8400 m-FCBGA 000010676h 2.26/1.6/0.8 1066 2.40 6,11,12 SLB3Q P8400 m-FCPGA 000010676h 2.26/1.6/0.8 1066 2.40 26,8,9 SL3BV P8600 m-FCBGA 000010676h 2.40/1.6/0.8 1066 2.53 6,11,12 SL3BU P8400 m-FCBGA 000010676h 2.26/1.6/0.8 1066 2.40 6,11,12...
  • Page 11 00001067Ah 1.4/1.2/0.8 34,13 NOTES: Does not support Intel® Dynamic Acceleration Technology Vcc core VID=1.000-1.250/0.850-1.250 V [HFM/LFM]; 0.750-0.925 V [S-LFM] Vcc core VID=0.650-0.859/0.600-0.850/0.350-0.700 V [C4/DC4/C6] Vcc core VID=1.000-1.300 [IDAT] Vcc core VID=1.000-1.275/0.850-1.100 V [HFM/LFM]; 0.800-1.000 V [S-LFM] Vcc core VID=0.650-0.850/0.600-0.850/0.35-0.70 V [C4/DC4/C6] This part is screened to avoid Erratum AZ52 Vcc core VID=1.050-1.1625/1.000 V [HFM/LFM];...
  • Page 12 Identification Information 26. Vcc core VID=0.725-0.775/0.725-0.750/0.400-0.700 V [C4/DC4/C6] 27. Vcc core VID=0.900-1.2125/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM] 28. Vcc core VID=0.900-1.275 [IDAT] 29. Vcc core VID=0.900-1.175/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM] 30. Vcc core VID=0.90-1.25 [IDAT] 31. Vcc core VID=0.775-1.100/0.80-0.975 V [HFM/LFM]; 0.750-0.925 V [S-LFM] 32.
  • Page 13: Summary Tables Of Changes

    Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed CPU steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 14 Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90- nm process technology R = Intel® Pentium® 4 processor on 90 nm process S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) T = Mobile Intel® Pentium® 4 processor–M U = 64-bit Intel®...
  • Page 15 AT = Intel® Celeron® processor 200 series AU = Intel® Celeron® Dual Core processor T1400 AV = Intel® Core™2 Extreme processor QX9000 sequence and Intel® Core™2 Quad processor Q9000 sequence processor AW = Intel® Core™ 2 Duo AX =Quad-Core Intel® Xeon® processor 5400 series AY =Dual-Core Intel®...
  • Page 16 Summary Tables of Changes Errata Steppings Number Status ERRATA No Fix EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB Shootdown No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions No Fix Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads No Fix Non-Temporal Data Store May be Observed in Wrong...
  • Page 17 Summary Tables of Changes Steppings Number Status ERRATA AZ20 No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown AZ21 No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation AZ22 No Fix Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate AZ23...
  • Page 18 Summary Tables of Changes Steppings Number Status ERRATA AZ40 No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations AZ41 Plan VM Exit with Exit Reason "TPR Below Threshold" Can Cause the Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field AZ42 No Fix...
  • Page 19 LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode AZ68 No Fix When Intel® Deep Power-Down State is Being Used, IA32_FIXED_CTR2 May Return Incorrect Cycle Counts AZ69 No Fix Enabling PECI via the PECI_CTL MSR Incorrectly...
  • Page 20 Summary Tables of Changes Number SPECIFICATION CLARIFICATIONS Clarification of Translation Lookaside Buffers (TLBS) Invalidation CPUID Instruction Will Return Brand String With a Missing Letter Number DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. § Specification Update...
  • Page 21: Errata

    Intel has not identified any operating systems that inspect the arithmetic portion of the EFLAGS register during a page fault nor observed this erratum in laboratory testing of software applications.
  • Page 22 Software that uses non-temporal data without proper serialization before accessing the Implication: non-temporal data may observe data in wrong program order. Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, “Buffering of Write Combining Memory Locations” section will operate correctly.
  • Page 23 Errata AZ5. Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault If code segment limit is set close to the end of a code page, then due to this erratum the Problem: memory page Access bit (A bit) may be set for the subsequent page prior to general protection fault on code segment limit.
  • Page 24 The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be Implication: lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 25 0x0. This is a rare condition that may result in a system hang. Intel has not observed this Implication: erratum with any commercially available software, or system.
  • Page 26 Errata AZ13. A Write to an APIC Register Sometimes May Appear to Have Not Occurred With respect to the retirement of instructions, stores to the uncacheable memory-based Problem: APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g., CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the actual priority has been lowered.
  • Page 27 Problem: Developer's Manual, Volume 3A section “Out-of-Order Stores for String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS...
  • Page 28 Interrupt or Exception (e.g., NMI (Non-Maskable Interrupt), Debug break (#DB), Machine Check (#MC), etc.) Operating systems may observe a #GP fault being serviced before higher priority Implication: Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 29 Errata AZ20. EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after Shutdown When the processor is going into shutdown due to an RSM inconsistency failure, EFLAGS, Problem: CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be asserted. This may be observed if the processor is taken out of shutdown by NMI#.
  • Page 30 If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in Implication: unpredictable system behavior. Intel has not observed this behavior in commercially available software. Workaround: SMM software should not change the value of EFLAGS.VM in SMRAM.
  • Page 31 While in 64-bit mode, with count greater or equal to 248, repeat string operations Implication: CMPSB, LODSB or SCASB may terminate without completing the last iteration. Intel has not observed this erratum with any commercially available software. Workaround: Do not use repeated string operations with RCX greater than or equal to 2 Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 32 STI instruction is executed. Because of this erratum, if following STI, an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel SpeedStep® Technology transitions or Thermal Monitor 1 events occur, the pending #MF may be serviced before higher priority interrupts.
  • Page 33 Exposure to this problem requires the use of a data write which spans a cache line boundary. This erratum may cause loads to be observed out of order. Intel has not observed this Implication: erratum with any commercially available software or system.
  • Page 34 Implication: to which features are actually supported. Workaround: Software should use the recommended enumeration mechanism described in the Architectural Performance Monitoring section of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3: System Programming Guide. Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 35 Errata AZ35. B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly Problem: cleared when the following sequence happens: 1. POP instruction to SS (Stack Segment) selector; 2.
  • Page 36 A livelock may be observed in rare conditions when instruction fetch causes multiple level Problem: one data cache snoops. Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum.
  • Page 37 Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field As specified in Section, “VM Exits Induced by the TPR Shadow”, in the Intel® 64 and IA- Problem: 32 Architectures Software Developer's Manual, Volume 3B, a VM exit occurs immediately after any VM entry performed with the “use TPR shadow”, “activate secondary controls”,...
  • Page 38 WC memory operations. Intel has not observed this erratum with any commercially-available software. Workaround: None identified. Intel does not support the use of cacheable and WC memory type aliasing, and WC operations are defined as weakly ordered.
  • Page 39 Under some rare conditions, when multiple streaming load instructions (MOVNTDQA) are Problem: mixed with non-streaming loads that split across cache lines, the processor may hang. Under the scenario described above, the processor may hang. Intel has not observed this Implication: erratum with any commercially available software.
  • Page 40 Implication: pipeline may not be detected/modified, and could retire without detection. Alternatively the instruction may cause a Machine Check Exception. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
  • Page 41 If a benign exception occurs while attempting to call the double-fault handler, the Implication: processor may hang or may handle the benign exception. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 42 Some processors may unexpectedly assert a false THERMTRIP# after a warm reset under Problem: certain environmental and operating conditions. Intel has observed this on a limited number of parts when they are operating at a core-to-bus ratio different from the ratio used at power-on.
  • Page 43 Errata AZ53. Short Nested Loops That Span Multiple 16-Byte Boundaries May Cause a Machine Check Exception or a System Hang Under a rare set of timing conditions and address alignment of instructions in a short Problem: nested loop sequence, software that contains multiple conditional jump instructions and spans multiple 16-byte boundaries, may cause a machine check exception or a system hang.
  • Page 44 [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially available software, or system. Workaround: As recommended in the IA32 Intel® Architecture Software Developer‟s Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception.
  • Page 45 In general, VMM software that follows the guidelines given in the section “Handling VM Implication: Exits Due to Exceptions” of Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide should not be affected. If the erratum improperly causes indication of blocking by STI or by MOV SS, the ability of a VMM to inject an interrupt may be delayed by one instruction.
  • Page 46 In the event of a thermal event while a processor is waking up from Intel Deep Power- Implication: Down State, the processor will initiate an appropriate throttle response. However, the associated thermal interrupt generated may be lost.
  • Page 47 VMCS, VM entry may fail as described in Section “VM-Entry Failures During or After Loading Guest State” of Intel® 64 and IA-32 Architectures Software Developer‟s Manual Volume 3B: System Programming Guide, Part 2. (The exit reason will be 80000021H and the exit qualification will be zero.) Note that the...
  • Page 48 Implication: the processor subsequently receives an INIT reset, the SYSCALL instructions will not behave as intended. Intel has not observed this erratum in any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
  • Page 49 When the processor is operating at an N/2 core to front side bus ratio, after exiting an Problem: Intel Deep Power-Down state, the internal increment value for IA32_FIXED_CTR2 MSR (Fixed Function Performance Counter 2, 30BH) will not take into account the half ratio setting.
  • Page 50 Implication: unless software explicitly examines the CS segment register between enabling protected mode and the first far JMP. Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode" recommends the far JMP immediately follows the write to CR0 to enable protected mode.
  • Page 51 Execution of the stores in XSAVE, when XSAVE is used to store SSE context only, may Implication: not follow program order and may execute before older stores. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 52 It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes AZ77. Intel Trusted Execution Technology ACM Revocation SINT ACM GM45_GS45_PM45_SINIT_21.BIN or Earlier are revoked and will not launch Problem: with the processor configuration information.
  • Page 53: Specification Changes

    Specification Changes Specification Changes There are no specification changes for this specification update revision. § Specification Update...
  • Page 54: Specification Clarifications

    When the brand strings of the Intel Core 2 Extreme Quad Core Mobile Processor, Intel Core 2 Duo Mobile Processor in SFF Package and Intel Core 2 Solo Mobile Processor in SFF Package are displayed, one less character in the processor number will be shown.
  • Page 55 Specification Clarifications Intel collateral will continue to show the correct and full processor number (with the first letter „S‟ or letter „X‟). Table 1. Documentation Clarification Processor Number in Datasheet Processor Number in Brand String Displayed SP9400 P9400 SP9300 P9300...
  • Page 56: Documentation Changes

    Documentation Changes Documentation Changes There are no documentation changes for this specification update revision. § Specification Update...

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