Dmasts; D.22 Dmasts - Intel 386 User Manual

D.22 DMASTS

DMA Status

DMASTS

(read only)
7
— —
Bit Number Bit Mnemonic
7–6 —
5 R1
4 R0
3–2 —
1 TC1
0 TC0
R1 R0
Reserved. These bits are undefined.
Request 1:
When set, this bit indicates that channel 1 has a hardware request
pending. When the request is removed, this bit is cleared.
Request 0:
When set, this bit indicates that channel 0 has a hardware request
pending. When the request is removed, this bit is cleared.
Reserved. These bits are undefined.
Transfer Complete 1:
When set, this bit indicates that channel 1 has completed a buffer
transfer (either its byte count expired or it received an EOP# input).
Reading this register clears this bit and clears TC1 in DMAIS.
Transfer Complete 0:
When set, this bit indicates that channel 0 has completed a buffer
transfer (either its byte count expired or it received an EOP# input).
Reading this register clears this bit and clears TC0 in DMAIS.
SYSTEM REGISTER QUICK REFERENCE
Expanded Addr: F008H
ISA Addr: 0008H
Reset State: 00H
— —
Function
0
TC1 TC0
D-27