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Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification

Intel core 2 extreme quadcore processor qx6000δ sequence and intel core 2 quad processor q6000δ sequence; on 65 nm process in the 775-land lga package supporting intel 64 architecture and intel virtualization technology, specification update
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®
Intel
Core™2 Extreme Quad-
Core Processor QX6000
Sequence and Intel
Quad Processor Q6000
Specification Update
— on 65 nm Process in the 775-land LGA Package supporting
®
Φ
Intel
64
Architecture and Intel
December 2010
®
Notice: The Intel
Core™2 Extreme quad-core processor and Intel
processor may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are
documented in this Specification Update.
Δ
®
Core™2
Δ
Sequence
®
Virtualization Technology±
®
Core™2 quad
Document Number:
315593-027

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  Also See for Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor

Intel Q9450 - Core 2 Quad Quad-Core Processor Design Manual
Intel Q9450 - Core 2 Quad Quad-Core Processor Design Manual 124 pages
Intel BX80562QX6700 - Core 2 Extreme 2.66 GHz Processor Datasheet
Intel BX80562QX6700 - Core 2 Extreme 2.66 GHz Processor Datasheet 98 pages

  Related Manuals for Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor

  Summary of Contents for Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor

  • Page 1 December 2010 ® ® Notice: The Intel Core™2 Extreme quad-core processor and Intel Core™2 quad processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
  • Page 2 DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

  • Page 3: Table Of Contents

    Summary Tables of Changes ....................8 Identification Information ....................18 Component Identification Information ..................19 Errata ..........................21 Specification Changes ......................67 Specification Clarifications ....................68 Documentation Changes ...................... 69 Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ Sequence and Intel ®...
  • Page 4 • Removed Erratum AK83 as duplicate and replaced with new erratum. -002 December 2006 • Updated Erratum AK75 and AK85 • Added Erratum AK88 – AK90 ® • Updated document title to include Intel Core™2 Quad processor Q6600 January 2007 -003 Out Of Cycle ®...
  • Page 5 • Added Erratum AK126, AK127 July 2009 -026 • Added Erratum AK128 March 16, 2010 December 8th, -027 • Added Erratum AK129 2010 Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ Sequence and Intel ® Core™2 Quad Processor Q6000 Δ...

  • Page 6: Preface

    Manual Volume 3A: System Programming Guide ® Intel 64 and IA-32 Architecture Software Developer’s Manual Volume 3B: System Programming Guide ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 7 Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.). § Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ Sequence and Intel ®...

  • Page 8: Summary Tables Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 9 Summary Tables of Changes Item Numbering Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor specification updates: ® ® Dual-Core Intel Xeon processor 7000 sequence ®...
  • Page 10 ® ® The Specification Updates for the Pentium processor, Pentium Pro processor, and other Intel products do not use this convention. Plan ERRATA Writing the Local Vector Table (LVT) when an Interrupt is No Fix Pending May Cause an Unexpected Interrupt...
  • Page 11 AK24 No Fix The PECI Controller Resets to the Idle State Some Bus Performance Monitoring Events May Not Count AK25 No Fix Local Events under Certain Conditions Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ Sequence and Intel ® Core™2 Quad Processor Q6000 Δ...
  • Page 12 Concurrent Multi-processor Writes to Non-dirty Page May AK43 Fixed Result in Unpredictable Behavior Performance Monitor IDLE_DURING_DIV (18h) Count May AK44 Fixed Not be Accurate ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 13 Fixed Programmed to Cause VM Exit to Return to a Different Mode IRET under Certain Conditions May Cause an Unexpected AK67 No Fix Alignment Check Exception Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ Sequence and Intel ® Core™2 Quad Processor Q6000 Δ...
  • Page 14 AK86 No Fix Incorrect Values Fault on ENTER Instruction May Result in Unexpected Values AK87 No Fix on Stack Frame ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 15 #GP due to WRMSR to an MTRR Mask PMI While LBR Freeze Enabled May Result in Old/Out-of- AK107 No Fix date LBR Information Overlap of an Intel ® VT APIC Access Page in a Guest with AK108 Fixed the DS Save Area May Lead to Unpredictable Behavior Intel ®...
  • Page 16 That Uses 32-Bit Address Size in 64-bit Mode A 64-bit Register IP-relative Instruction May Return AK129 No Fix Unexpected Results ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 17 Number SPECIFICATION CLARIFICATIONS There are no Specification Clarifications in this Specification Update revision. Number DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. § Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ Sequence and Intel ® Core™2 Quad Processor Q6000 Δ...

  • Page 18: Identification Information

    Identification Information Identification Information ® Figure 1. Intel Core™2 Extreme quad-core processor Package INTEL ©'05 QX6700 INTEL® CORE™2 EXTREME SLxxx [COO] 2.66GHZ/8M/1066/05B [FPO] ATPO ® Figure 2. Intel Core™2 quad processor Package INTEL ©'05 Q6600 INTEL® CORE™2 QUAD SLxxx [COO] 2.40GHZ/8M/1066/05B...

  • Page 19: Component Identification Information

    Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to the Intel Processor Identification and the CPUID Instruction Application Note (AP-485) Conroe and Woodcrest Processor Family BIOS Writer’s Guide (BWG)
  • Page 20 8. These parts support Thermal Monitor 2 (TM2) feature. 9. These parts have PECI enabled. ® 10. These parts have Enhanced Intel SpeedStep Technology (EIST) enabled 11. These parts have Extended HALT State (C1E) enabled. 12. These processors require ALCT thermal solution.

  • Page 21: Errata

    DEFER# is received during a snoop phase and the Locked transaction is pipelined on the front side bus (FSB), LOCK# may unexpectedly de-assert. Implication: When this erratum occurs, the system may hang during shutdown. Intel has not observed this erratum with any commercially available systems or software.
  • Page 22 SYSCALL instruction). Due to this erratum, the RFLAGS.RF bit will be unconditionally cleared after execution of the SYSRET instruction. ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 23 Errata Implication: The SYSRET instruction can not be used if the RF flag needs to be set after returning from a system call. Intel has not observed this erratum with any commercially available software. Workaround: Use the IRET instruction to return from a system call, if RF flag has to be set after the return.
  • Page 24 When programming DTS value, the previous DTS threshold may be crossed. This will generate an unexpected thermal interrupt. ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 25 • VMLAUNCH and VMRESUME instructions are not counted. • HLT and MWAIT instructions are not counted. The following instructions, if executed during HLT or MWAIT events, are also not counted: Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ...
  • Page 26 A20M# is normally only used with the first megabyte of memory. For the steppings affected, see the Summary Tables of Changes. Status: ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 27 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system.
  • Page 28 (falling through from address 00007fffffffffff to non- canonical address 0000800000000000), under some circumstances the code fetch will be converted to a canonical fetch at address ffff800000000000. ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 29 AK23. VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field ® Processors supporting Intel Virtualization Technology can execute VMCALL Problem: from within the Virtual Machine Monitor (VMM) to activate dual-monitor treatment of SMIs and SMM. Due to this erratum, if reserved bits are set to values inconsistent with VMX Capability MSRs, VMCALL may not VMFail.
  • Page 30 ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 31 (such as interrupts) will cause the (E)CX registers to be increment by a value that corresponds to 64K bytes for 16 bit address size and 4G bytes for 32 bit address size. Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ...
  • Page 32 Errata Implication: (E)CX may contain an incorrect count which may cause some of the MOVS or STOS operations to re-execute. Intel has not observed this erratum with any commercially available software. Workaround: Do not use values in (E)CX that when multiplied by the data size give values larger than the address space size (64K for 16-bit address size and 4G for 32-bit address size).
  • Page 33 Implication: In this case, the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, including a General Protection Fault (GPF) or other unexpected behaviors.
  • Page 34 (alignment <= 0x10h), and one of the following conditions is satisfied: 1) 32-bit addressing, obtained by using address-size override, when in 64-bit mode ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 35 PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions may Problem: not be executed when Alignment Check is enabled. Implication: PREFETCH instructions may not perform the data prefetch if Alignment Check is enabled. Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ Sequence and Intel ®...
  • Page 36 Implication: The counter may reflect a value higher or lower than the actual number of events. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 37 #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume from System Management Mode) returns to Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ...
  • Page 38 (e.g. NMI (Non-Maskable Interrupt), Debug break (#DB), Machine Check (#MC), etc.) Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None Identified.
  • Page 39 Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially available software, or system.
  • Page 40 Implication: This erratum may lead to livelock, shutdown or other unexpected processor behavior. Intel has not observed this erratum with any commercially available system. Workaround: None identified.
  • Page 41 , repeat string operations CMPSB, LODSB or SCASB may terminate without completing the last iteration. Intel has not observed this erratum with any commercially available software. Workaround: Do not use repeated string operations with RCX greater than or equal to 2 For the steppings affected, see the Summary Tables of Changes.
  • Page 42 This can occur even if the fault causes a VM exit or if its delivery causes a nested fault. ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 43 Errata Implication: None identified. Although the EFLAGS value saved may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without a page fault.
  • Page 44 • FADD and FMUL instructions with a NaN(Not a Number) operand and a memory operand • FDIV instruction with zero operand value in memory ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 45 Monitoring Interrupt) should be issued. Due to this erratum, the PMI may be delayed by one PEBS event. Implication: Debug Store Interrupt Service Routines may observe delay of PMI occurrence by one PEBS event. Workaround: None identified. Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ Sequence and Intel ®...
  • Page 46 Workaround: Use an interrupt task gate for the machine check handler. For the steppings affected, see the Summary Tables of Changes. Status: ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...

  • Page 47: Software Interrupts

    Debug-Exceptions Field of the Guest State Area will be Incorrectly Set by VM Exit on a MOV to CR8 Instruction ® In a system supporting Intel Virtualization Technology, the BS bit (bit 14 of Problem: the Pending-Debug-Exceptions field) in the guest state area will be incorrectly set when all of the following conditions occur: The processor is running in VMX non-root as a 64 bit mode guest;...
  • Page 48 L2 written by another core, while the second load will get the data straight from the WT Store. ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 49 16 bit operand size (REX.W =0 and 66H prefix) will only store 16 bits and leave bits 63:16 at the destination register unmodified, instead of storing zeros in them. Implication: Intel has not observed this erratum with any commercially available software. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes.
  • Page 50 Basic Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially available software.
  • Page 51 A or D bits being set in a Page Table Entry (PTE)) Implication: Stale translations may remain valid in TLB after a PTE update resulting in unpredictable system behavior. Intel has not observed this erratum with any commercially available software.
  • Page 52 (due to redundant prefixes placed before the instruction) may lead, under complex circumstances, to unexpected behavior. Implication: The processor may behave unexpectedly due to invalid instructions. Intel has not observed this erratum with any commercially available software.
  • Page 53 • the EFLAGS register are set Implication: If this erratum occurs the stack size may be incorrect, consequently this may result in unpredictable system behavior. Intel has not observed this erratum with any commercially available software. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes.
  • Page 54 Even if the BR1# and Lock# terminations are always on or always off, VOL electrical specifications are not violated. Intel has not observed any functional failure due to this erratum. Workaround: None identified.
  • Page 55 Workaround: Calculate the ratio of the rates at which the TSC and the CPU_CLK_UNHALTED.REF performance monitoring event count (this can be done by measuring simultaneously their counted value while executing code) Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ...
  • Page 56 Workaround: Software can avoid this erratum by not using REP STOS/MOVS store operations within the monitored address range. ® Δ Intel Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Specification Update...
  • Page 57 As an example, an access to a memory mapped I/O device may be incorrectly marked as cacheable, become cached, and never make it to the I/O device. Intel has not observed this erratum with any commercially available software.
  • Page 58 APIC access page to avoid such an overlap. Under normal circumstances for correctly written software, such an overlap is not expected to exist. Intel has not observed this erratum with any commercially available software. Workaround: For a fully comprehensive workaround, the VMM should not allow the logging of branch or PEBS records while guest software is running if the "virtualize...
  • Page 59 Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
  • Page 60 Problem: multiple level one data cache snoops. Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum.
  • Page 61 Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field ® As specified in Section, “VM Exits Induced by the TPR Shadow”, in the Intel Problem: 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, a VM exit occurs immediately after any VM entry performed with the “use TPR...
  • Page 62 WC memory operations. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Intel does not support the use of cacheable and WC memory type aliasing, and WC operations are defined as weakly ordered.
  • Page 63 Implication: If a benign exception occurs while attempting to call the double-fault handler, the processor may hang or may handle the benign exception. Intel has not observed this erratum with any commercially available software.
  • Page 64 Implication: In general, VMM software that follows the guidelines given in the section ® “Handling VM Exits Due to Exceptions” of Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide should not be affected. If the erratum improperly causes indication of blocking by STI or by MOV SS, the ability of a VMM to inject an interrupt may be delayed by one instruction.
  • Page 65 Implication: Software may erroneously infer that a page fault was due to a reserved-bit violation when it was actually due to an attempt to access a not-present page. Intel has not observed this erratum with any commercially available software. Workaround: Page-fault handlers should ignore the RSVD flag in the error code if the P flag is 0.
  • Page 66 FP load around a 4-Gbyte boundary in this way is not a normal programming practice. Intel has not observed this erratum with any commercially available software. Workaround: If the FP Data Operand Pointer is used in a 64-bit operating system which may run code accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP accesses are wrapped around a 4-Gbyte boundary.

  • Page 67: Specification Changes

    64 and IA-32 Architectures Software Developer’s Manual volumes 1, 2A, 2B, • 3A, and 3B All Specification Changes will be incorporated into a future version of the appropriate ® ® Intel Core™2 Extreme Quad-Core processor and Intel Core™2 Quad processor Datasheet documentation. § Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ...

  • Page 68: Specification Clarifications

    64 and IA-32 Architectures Software Developer’s Manual volumes 1, 2A, 2B, 3A, and 3B All Specification Clarifications will be incorporated into a future version of the ® ® appropriate Intel Core™2 Extreme Quad-Core processor and Intel Core™2 Quad processor Datasheet documentation. § ® Δ...

  • Page 69: Documentation Changes

    64 and IA-32 Architectures Software Developer’s ® Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document Intel 64 and IA-32 Architectures Software Developer’s manual documentation changes. Follow the link below to become familiar with this file.

This manual is also suitable for:

Core 2 extreme qx6800Core 2 extreme qx6700Core 2 extreme qx6850Core 2 quad q6600Core 2 quad q6700