6.3.4
6.3.5
Halt/Shutdown Cycle ...............................................................................................6-26
6.3.6
Refresh Cycle .........................................................................................................6-28
6.3.7
BS8 Cycle ...............................................................................................................6-31
6.3.7.1
Write Cycles .......................................................................................................6-31
6.3.7.2
Read Cycles .......................................................................................................6-31
6.4
BUS LOCK................................................................................................................... 6-34
6.4.1
Locked Cycle Activators ..........................................................................................6-34
6.4.2
Locked Cycle Timing ...............................................................................................6-34
6.4.3
LOCK# Signal Duration ...........................................................................................6-35
6.5
6.5.1
HOLD/HLDA Timing ................................................................................................6-36
6.5.2
HOLD Signal Latency .............................................................................................6-37
6.6
DESIGN CONSIDERATIONS...................................................................................... 6-38
6.6.1
6.6.1.1
System Configuration .........................................................................................6-39
6.6.1.2
6.6.2
SRAM/FLASH Interface ..........................................................................................6-41
6.6.3
PSRAM Interface ....................................................................................................6-42
6.6.4
Paged DRAM Interface ...........................................................................................6-43
6.6.5
CHAPTER 7
7.1
7.2
SMM HARDWARE INTERFACE ................................................................................... 7-1
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.2.1
SMI# Priority .........................................................................................................7-7
7.3.2.2
7.3.2.3
HALT Restart .......................................................................................................7-9
7.3.2.4
7.3.2.5
I/O Restart ..........................................................................................................7-10
7.3.3
7.3.3.1
7.3.3.2
7.3.3.3
7.3.3.4
7.3.4
SMRAM Programming ............................................................................................7-12
7.3.4.1
CONTENTS
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