I/O Port Registers; Register Definitions - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL

16.2 REGISTER DEFINITIONS

Each port has three control registers and a status register associated with it (Table 16-2). The con-
trol registers (PnCFG, PnDIR, and PnLTC) can be both read and written. The status register (Pn-
PIN) can only be read. All four registers reside in I/O address space.
Register Address
P1CFG 0F820H
P2CFG 0F822H
P3CFG 0F824H
(read/write)
P1DIR 0F864H
P2DIR 0F86CH
P3DIR 0F874H
(read/write)
P1LTC 0F862H
P2LTC 0F86AH
P3LTC 0F872H
(read/write)
P1PIN 0F860H
P2PIN 0F868H
P3PIN 0F870H
(read only)
16-6
Table 16-2. I/O Port Registers
Port n Mode Configuration:
Each bit controls the mode of the associated pin.
0 = Selects I/O mode.
1 = Selects peripheral mode.
Port n Direction:
Each bit controls the direction of a pin that is in I/O mode.
0 = Configures a pin as a complementary output. If a pin is in peripheral
mode, this value is ignored.
1 = Configures a pin as either an input or an open-drain output.
Port n Data Latch:
Each bit contains data to be driven onto an output pin that is in I/O mode. Write
the desired pin state value to this register. If a pin is in peripheral mode, this
value is ignored.
Reading this register returns the value in the register—not the actual pin state.
Port n Pin State:
Each bit of this read-only register reflects the state of the associated pin.
Reading this register returns the current pin state value, regardless of the pin's
mode and direction.
Description