Configuration Of Dma, Bus Arbiter, And Refresh Unit - Intel 386 User Manual

DMACFG.2:0
DMA
DREQ0
DMACFG.3
DMAACK0#
DMACFG.6:4
DREQ1
DMACFG.7
DMAACK1#
DMAINT
End of Process
HOLD
Bus Arbiter
To
Core
HOLD
HLDA
Refresh Unit
From
REFRESH#
Core
HLDA
† Alternate pin signals are in parentheses.
Figure 5-2. Configuration of DMA, Bus Arbiter, and Refresh Unit
3
0
RBFDMA0 (SIO0)
1
TXEDMA1 (SIO1)
2
3 SSTBE (SSIO)
4 OUT1 (TCU)
5 RBFDMA1 (SIO1)
6
TXEDMA0 (SIO0)
7
SSRBF (SSIO)
3
0
RBFDMA1 (SIO1 )
1
2 TXEDMA0 (SIO0)
SSRBF (SSIO)
3
OUT2 (TCU)
4
5
RBFDMA0 (SIO0)
6
TXEDMA1 (SIO1)
7
SSTBE (SSIO)
To ICU
To/From I/O Port 1
To/From I/O Port 1
DEVICE CONFIGURATION
To SIO1
PINCFG.4
0
From CSU
1
To SIO1
PINCFG.2
0
From SIO1
1
PINCFG.3
0
From SIO1
1
P1CFG.6
1
0
P1CFG.7
1
0
PINCFG.6
1
From CSU
0
DRQ0
(DCD1#)†
DACK0#
(CS5#)
DRQ1
(RXD1)
DACK1#
(TXD1)
EOP#
(CTS1#)
HOLD
(P1.6)
HLDA
(P1.7)
REFRESH#
(CS6#)
A2516-02
5-5