Operation Command Word 1 (Ocw1) - Intel 386 User Manual

9.3.7

Operation Command Word 1 (OCW1)

OCW1 is the interrupt mask register. Setting a bit in the interrupt mask register disables (masks)
interrupts from the corresponding IR signal. For example, setting the master's OCW1 M3 bit dis-
ables interrupts from the master IR3 signal. Clearing a bit in the interrupt mask register enables
interrupts from the corresponding IR signal.
Operation Command Word 1
OCW1 (master and slave)
(read/write)
7
M7 M6
Bit Bit
Number Mnemonic
7–0 M7:0
NOTE: The 8259A must be initialized before it can be used. After reset, the 8259A register states are
undefined. The 8259A modules must be initialized before the IF flag in the core FLAG register is
set.
Figure 9-13. Operation Command Word 1 (OCW1)
M5 M4
Mask IR:
0 = Enables interrupts on the corresponding IR signal.
1 = Disables interrupts on the corresponding IR signal.
NOTE: Setting the mask bit does not clear the respective interrupt
pending bit.
INTERRUPT CONTROL UNIT
master
Expanded Addr: F021H
ISA Addr: 0021H
Reset State: XXH
M3 M2 M1
Function
slave
F0A1H
00A1H
XXH
0
M0
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