Wdtstatus; D.74 Wdtstatus - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL

D.74 WDTSTATUS

WDT Status

WDTSTATUS

(read/write)
7
WDTEN —
Bit Bit
Number Mnemonic
7 WDTEN
6–2 —
1 BUSMON
0 CLKDIS
.
D-70
— —
Watchdog Mode Enabled:
This read-only bit indicates whether watchdog mode is enabled. Only a
lockout sequence can set this bit and only a device reset can clear it.
0 = Watchdog mode disabled
1 = Watchdog mode enabled
Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
Bus Monitor Enable:
0 = Disables bus monitor mode
1 = Enables bus monitor mode
Read this bit to determine the current status. A lockout sequence clears
BUSMON and prevents writes to the WDTSTATUS register.
Clock Disable:
Write to this bit to stop or restart the clock to the WDT; read it to
determine the current clock status. A lockout sequence clears CLKDIS
and prevents writing to this register.
0 = Clock enabled
1 = Processor clock (frequency=CLK2/2) disabled (stopped)
Expanded Addr: F4CAH
ISA Addr: —
Reset State: 00H
— — BUSMON
Function
0
CLKDIS