Tracing Data - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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Address
4031 D024h
4031 D028h
4031 D02Ch
4031 D030h
4031 D034h
4031 D038h
4031 D03Ch
(*) the default handlers for pre-fetch and data abort are performing reads from CP15 debug registers to
retrieve the reason of the abort:
• In case of pre-fetch abort: the IFAR register is read from CP15 and stored into R0. The IFSR
register is read and stored into the R1 register. Then the ROM Code jumps to the pre-fetch abort
dead loop (20088h).
• In case of data abort: the DFAR register is read from CP15 and stored into R0. The DFSR register
is read and stored into the R1 register. Then the ROM Code jumps to the data abort dead loop
(2008Ch).

21.3.2.4 Tracing Data

Thissection contains trace vectors reflecting the execution path of the public boot.
describes the usage of the different trace vectors and lists all the possible trace codes.
Address
4031 D040h
4031 D044h
4031 D048h
4031 D04Ch
4031 D050h
4031 D054h
4031 D058h
4031 D05Ch
4031 D060h
4031 D064h
21.3.2.5 Static Variables
This area contains the ROM code static variables used during boot time (and possibly during run-time,
if calling the Public ROM API functions).
SPRUGX9 – 15 April 2011
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Preliminary
Table 21-5. RAM Exception Vectors (continued)
Exception
Undefined
SWI
Pre-fetch abort
Data abort
Unused
IRQ
FIQ
Table 21-6. Tracing Data
Size [bytes]
4
4
4
4
4
4
4
4
4
4
© 2011, Texas Instruments Incorporated
Content
20080h
20084h
Address of default pre-fetch abort handler (*)
Address of default data abort handler (*)
20090h
Address of default IRQ handler
20098h
Description
Current tracing vector, word 1
Current tracing vector, word 2
Current tracing vector, word 3
Current copy of the PRM_RSTST register (reset reasons)
Cold reset run tracing vector, word 1
Cold reset run tracing vector, word 2
Cold reset run tracing vector, word 3
Reserved
Reserved
Reserved
ROM Code Memory and Peripheral Booting
Memory Map
Section 21.12
1993