Pins Used For Nandi2C Boot For I2C Eeprom Access; Nand Geometry Information On I2C Eeprom - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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Item Description
Cell type 2 levels
4 levels
8 levels
16 levels
Block Size 64kB
128kB
256kB
512kB
• Reading NAND geometry from I2C EEPROM. ROM supports a special boot mode called
NANDI2C to support NAND devices whose geometry cannot be detected by the ROM automatically
using methods described in the previous section
ROM code tries to read NAND geometry from an I2C EEPROM. If the read is successful, ROM
code then proceeds to next steps of NAND boot, beginning with reading bad blocks information.
The list of pins that are configured by the ROM incase of NANDI2C boot mode (This is in addition to
the NAND boot pins described in
Table 21-15. Pins used for NANDI2C boot for I2C EEPROM access
Signal name
I2C SCL
I2C SDA
ROM accesses the I2C EEPROM at I2C slave address 50h and reads 7 bytes starting from address
offset 80h. The format of this (NAND geometry information) is as follows:
Byte address
80h
81h
82h
83h
84h
85h
86h
• ECC correction. The default ECC correction applied is BCH 8b/sector using the GPMC and ELM
hardware.
For device ID codes D3h, C3h, D5h, C5h, D7h, C7h, DEh, CEh when manufacturer code (first ID
byte) is 98h the Cell type information is checked in the 4th byte of ID data. If it is equal to 10b then
the ECC correction applied is BCH 16b/sector.
The detection procedure is described in
the ROM Code changes GPMC to 16-bit bus width if necessary.
SPRUGX9 – 15 April 2011
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Preliminary
Table 21-14. 4th NAND ID Data Byte (continued)
7 6
Table 21-17).
Table 21-16. NAND Geometry Information on I2C EEPROM
Upper nibble
NAND column address (word/byte offset within a
page) size in bytes,
Example: 2
Page size (2N) exponent "N". Example (for page
size of 2048): 11
NAND bus width
0 → 8-bit, 1 → 16-bit
Figure
© 2011, Texas Instruments Incorporated
I/O #
5 4 3
0
0
1
1
0 0
0 1
1 0
1 1
(Figure 21-12). If this boot mode is selected, the
Pin used
iic0_scl
iic0_sda
Information
Magic Number – 10h
Magic Number – B3h
Magic Number – 57h
Magic Number – A6h
NAND row address (page offset) size in bytes.
Pages per block (2N) exponent "N"
Example (for number of blocks 64): 6
0→ No ECC, 1 → BCH8, 2 → BCH16
21-12. Once the device has been successfully detected,
ROM Code Memory and Peripheral Booting
Memory Booting
2 1 0
0
1
0
1
Lower nibble
Example: 3
ECC Type
2007