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Registers
20.9.6.1.10 Index Register for Selecting the Endpoint Status and Control Registers (USBn_INDEX)
Each TX endpoint and each Rx endpoint have their own set of control/status registers located between
Core_Offset 0x0100 – 0x01FF. In addition one set of TX control/status and one set of Rx control/status
registers appear at Core_Offset 0x0010 – 0x0019. This block of memory can be used as a proxy to
access endpoint configuration registers. Index is a 4-bit register that determines which endpoint
control/status registers are accessed.
Before accessing an endpoint's control/status registers at Core_Offset 0x0010 – 0x0019, the endpoint
number should be written to the Index register to ensure that the correct control/status registers appear
in the memory map.
The index register for selecting the endpoint status and control registers is shown in
described in
Table
Figure 20-154. Index Register for Selecting the Endpoint Status and Control Registers
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-170. Index Register for Selecting the Endpoint Status and Control Registers
Bits
Field Name
7-4
Reserved
3-0
EPSEL
1950
Universal Serial Bus (USB)
Preliminary
20-170.
4
R-0h
(USBn_INDEX) Field Descriptions
Description
Reserved
Each transmit endpoint and each receive endpoint have their own set of control/status registers.
EPSEL determines which endpoint control/status registers are accessed. Before accessing an
endpoint's control/status registers, the endpoint number should be written to the Index register to
ensure that the correct control/status registers appear in the memory-map.
© 2011, Texas Instruments Incorporated
(USBn_INDEX)
3
www.ti.com
Figure 20-154
0
EPSEL
R/W-0-Fh
SPRUGX9 – 15 April 2011
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