Hamming Code Accumulation Algorithm (1 Of 2); Ecc Enable Settings - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Architecture
Bit Field Register
ECCCS GPMC_ECC_CONFIG
ECC16B GPMC_ECC_CONFIG
ECCCLEAR GPMC_ECC_CONTROL
ECCPOINTER GPMC_ECC_CONTROL
ECCSIZE1 GPMC_ECC_SIZE_CONFIG
ECCSIZE0 GPMC_ECC_SIZE_CONFIG
ECCjRESULTSIZE GPMC_ECC_SIZE_CONFIG
(j from 1 to 9)
ECCENABLE GPMC_ECC_CONFIG
5.2.4.12.3.1.3 ECC Computation
The ECC algorithm is a multiple parity bit accumulation computed on the odd and even bit streams
extracted from the byte or Word 16 streams. The parity accumulation is split into row and column
accumulations, as shown in
used to compute the upper level row and column parities. Only the final computation of each parity bit is
used for ECC comparison and correction.
P1o = bit7 XOR bit5 XOR bit3 XOR bit1 on each byte of the data stream
P1e = bit6 XOR bit4 XOR bit2 XOR bit0 on each byte of the data stream
P2o = bit7 XOR bit6 XOR bit3 XOR bit2 on each byte of the data stream
P2e = bit5 XOR bit4 XOR bit1 XOR bit0 on each byte of the data stream
P4o = bit7 XOR bit6 XOR bit5 XOR bit4 on each byte of the data stream
P4e = bit3 XOR bit2 XOR bit1 XOR bit0 on each byte of the data stream
Each column parity bit is XORed with the previous accumulated value.
Figure 5-31. Hamming Code Accumulation Algorithm (1 of 2)
Row 0 Row 0 bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit7 bit6 bit5 bit4 bit3 bit2
Row 1 Row 1 bit7 bit6 bit5 bit4 bit3 bit2 bit7 bit6 bit5 bit4 bit3 bit2 bit7
Row 2 Row 2
bit7 bit6 bit5 bit4 bit3 bit2 bit7 bit7 bit6 bit5 bit4 bit3 bit2
Row 3 Row 3 bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit7 bit6 bit5 bit4 bit3 bit2
Row 252 Row 252
bit7 bit6 bit5 bit4 bit3 bit2 bit7 bit6 bit5 bit4 bit3 bit2 bit7
Row 253 Row 253
bit7 bit6 bit5 bit4 bit3 bit2 bit7 bit7 bit6 bit5 bit4 bit3 bit2
Row 254 Row 254 bit7 bit6 bit5 bit4 bit3 bit2 bit7 bit6 bit5 bit4 bit3 bit2 bit7
Row 255 Row 255
bit7 bit6 bit5 bit4 bit3 bit2 bit7 bit6 bit5 bit4 bit3 bit2 bit7
P1o P1o P1o
610
General-Purpose Memory Controller (GPMC)
Preliminary
Table 5-12. ECC Enable Settings
Figure 5-31 and
bit5 bit3 bit1 bit0 bit1 bit0 bit1
bit5 bit3 bit1 bit0 bit1 bit0 bit1
bit5 bit3 bit1 bit0 bit1 bit0 bit1
bit5 bit3 bit1 bit0 bit1 bit0 bit1
bit5 bit3 bit1 bit0 bit1 bit0 bit1
bit5 bit3 bit1 bit0 bit1 bit0 bit1
bit5 bit3 bit1 bit1 bit0 bit1 bit0
bit5 bit3 bit1 bit0 bit1 bit1 bit0
P1o P1o P1o P1o P1o P1o P1o P1o P1o
© 2011, Texas Instruments Incorporated
Value Comments
0-3h Selects the chip-select where ECC is computed
0/1 Selects column number for ECC calculation
0-7h Clears all ECC result registers
0-7h A write to this bit field selects the ECC result register where
the first ECC computation is stored. Set to 1 by default.
0-FFh Defines ECCSIZE1
0-FFh Defines ECCSIZE0
0/1 Selects the size of ECCn result register
1 Enables the ECC computation
Figure 5-32. The intermediate row and column parities are
Row 0 Row 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 1 Row 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7
Row 2 Row 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 3 Row 3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 252 Row 252
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 253 Row 253
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 254 Row 254
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7
Row 255 Row 255
bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
P1o P1o P1o
P2o P2o P2o
www.ti.com
bit5 bit3 bit2 bit1 bit0
bit5 bit3 bit2 bit1 bit0
bit5 bit3 bit2 bit1
bit5 bit3 bit2 bit1
bit5 bit3 bit1
bit5 bit3 bit1
bit5 bit3 bit1
bit5 bit3 bit1
P1o P1o P1o P1o P1o P1o P1o P1o P1o
P2o P2o P2o
SPRUGX9 – 15 April 2011
Submit Documentation Feedback