Section Iv. Theory Of Operation; General; Data Module Input Logic; Multiplexer - Texas Instruments 990 Maintenance Manual

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945407-9701
SECTION IV
THEORY OF OPERATION
4.1 GENERAL
This section provides the theory of operation of the 16 Input/16 Output TTL Data Module. A
general description of the data module is given in Section I and it should be read first if the
reader is not familiar with the basic data module operation. The detailed description in this
section is accompanied by timing diagrams and abbreviated logic diagrams. Detailed logic
diagrams may be found in the Model 990 Computer Family Maintenance Drawings Manual,
Manual Numbers 945421-9701 and 945421-9702.
4.2 DATA MODULE INPUT LOGIC
Refer to figure 4-1 for a diagram of the data module input logic, the associated timing diagram,
and the pin numbers used on the data module. As shown, the CPU provides the data module
with +5 V de and a common ground that can be tied in with the peripheral device. The 16
peripheral input lines are applied to the U3 multiplexer via individual emitter-follower transistors.
Capacitor pads are provided across the inputs for use when line noise is a problem. When the
user program decides to read one of the input lines, the CPU develops address select lines
(CRUBITl 2-15) which are decoded by the multiplexer (see table 4-1) and a data module enable
(IMODSELA-) that combine to select one of the 16 input lines. The input data is inverted three
times and passed to the CPU via the CRUBITIN- line. A low (0 to 1 V) or high (3 to 5 V) input
signal becomes a high (logic 1) or low (logic 0) logic level, respectively, in the CPU.
4.2.1 MULTIPLEXER. The multiplexer is a 16-to-l data selector (see figure 4-2) that passes one
of its inputs to a output gate each time it is strobed by IMODSELA- from the CPU. The input
passed is selected by the CRU address bits, CRUBIT12-15, as shown in table 4-1. Once passed to
the output of the multiplexer, the data is gated to the CPU if IMODSELA-
=
0.
4.3 DATA MODULE OUTPUT LOGIC
Refer to figure 4-3 for a diagram of the data module output logic, the associated timing
diagrams, and the pin numbers used on the module. -When a program is required to transfer data
from the CPU to an attached peripheral device, the CPU must supply the data module with an
output data bit (CRUBITOUT-), destination flip-flop select address (CRUBITl 2-15), a data
module enable signal (IMODSELA-), and a write clock signal (STORECLK-). The IMODSELA-
and STORECLK- signals combine to gate the data bit into the selected flip-flop. The
CR UBIT 12-15 signals are applied to the U 13 address decoder to select the destination flip-flop
(see table 4-2). The CPU output bit is inverted and stored in the selected flip-flop and then made
available to the attached peripheral after two more level inversions. The result of the three level
inversions is that a logic 1 (2.4 V) or a logic 0 (0.4 V) of computer output data becomes a low
voltage (0.4 V or less) or an open circuit, respectively, at the peripheral interface.
4.3.1 OUTPUT DECODER. The Ul3 output decoder is a 4-line-to-16-line decoder. As shown in
figure 4-4, it accepts the CRUBITl 2-15 inputs and the IMODSELA- and STORECLK- signals.
When IMODSELA- and STORECLK- are both low, the decoder reads the inputs and seiects the
appropriate output line.
4-1
Digital Systems Division .