Xilinx CAN FD v2.0 Product Manual
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Xilinx CAN FD v2.0 Product Manual

Xilinx CAN FD v2.0 Product Manual

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CAN FD v2.0
LogiCORE IP Product Guide
Vivado Design Suite
PG223 December 5, 2018

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Summary of Contents for Xilinx CAN FD v2.0

  • Page 1 CAN FD v2.0 LogiCORE IP Product Guide Vivado Design Suite PG223 December 5, 2018...

  • Page 2: Table Of Contents

    Simulating the Example Design............86 CAN FD v2.0...
  • Page 3 Finding Help on Xilinx.com ........

  • Page 4: Ip Facts

    FD protocol license before selling a device containing ® The Xilinx LogiCORE™ IP CAN with Flexible the Xilinx CAN FD IP core. Data Rate (CAN FD) core is ideally suited for automotive and industrial applications such as LogiCORE™ IP Facts Table...

  • Page 5: Other Features

    Snoop (Bus Monitoring) mode ° Sleep mode with Wake-Up Interrupt ° Internal Loopback mode ° Bus-Off Recovery mode ° Auto-Recovery User intervention for Auto-Recovery Disable Protocol Exception Event mode ° CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 6: Chapter 1: Overview

    CAN Clock Domain AXI Clock Domain X14811-081418 Figure 1-1: CAN FD Core Layered Architecture and Connectivity The core requires an external PHY to be connected to communicate on the CAN bus. Note: CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 7: Core Description

    CRC sequence calculation including stuff bit count for FD frames ° Bit rate switching ° • Reception of a serial bitstream from the PHY Deserialization and recompiling of the frame structure ° Bit destuffing ° CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 8: Licensing And Ordering

    CAN FD product web page. Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative. CAN FD v2.0...

  • Page 9: Chapter 2: Product Specification

    See the Vivado AXI Reference Guide (UG1037) s_axi_* S_AXI_LITE – – [Ref 7] for the description of the AXI4 signals. Clock, Interrupt, and PHY Signals (2)(3) ip2bus_intrevent Interrupt Active-High interrupt line. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 10: Register Space

    AXI Write Data Strobe (*_wstrb) signal. For write access, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 11 Data Phase Baud Rate Prescaler Register 0x008C DP_BTR Read, Write Data Phase Bit Timing Register 0x0090 Read, Write TX Buffer Ready Request Register Interrupt Enable TX Buffer Ready Request 0x0094 IETRS Read, Write Served/Cleared Register CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 12 Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 (Reset Value) 0x0000 RSVD SRR (0x0) 0x0004 RSVD RSVD MSR (0x0) CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 13 TIMESTAMP_CNT[15:0] RSVD TSR (0x0) 0x002C RSVD Reserved 0x0084 DP_BRPR 0x0088 RSVD TDCOFF [5:0] DP_BRP [7:0] (0x0) DP_SJW DP_TS2 DP_BTR 0x008C RSVD RSVD RSVD DP_TS1[4:0] [3:0] [3:0] (0x0) 0x0090 TRR (0x0) CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 14 RSVD Reserved 0x00DC RSVD Reserved 0x00E0 AFR (0x0) 0x00E4 RSVD Reserved 0x00E8 FL_1[6:0] RI_1[5:0] FL[6:0] RI[5:0] FSR (0x0) 0x00EC RSVD RXFP[4:0] RXFWM_1[5:0] RXFWM[5:0] (0xF) 0x00F0 RSVD Reserved 0x00F4 RSVD Reserved CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 15 CEN bit in the SRR is 0. Mode Select register bits (except SLEEP and SBR) can be changed only when the CEN bit is 0. If the CEN bit is changed during core operation, Xilinx recommends resetting the core so that operation starts over.
  • Page 16 • 0 = Makes the core transmit CAN FD frames as per BRS bit in the TX Message element. This bit can be written only when the CEN bit in SRR is 0. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 17 These bits indicate the prescaler value. BRP[7:0] The actual value is one more than the value written to the register. These bits can be written only when the CEN bit in SRR is 0. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 18 11 consecutive nominal recessive bits is seen. In SNOOP mode, error counters are disabled and cleared to 0. Reads to the Error Counter Note: register return 0. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 19 • 0 = Indicates CRC error has not occurred in Data Phase (Fast) data rate after the last write to this bit. If this bit is set, writing a 1 clears it. Reserved Reserved. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 20 1. In transmitter delay compensation phase, any error is reported as fast bit error (by the transmitter). 2. Fixed stuff bit errors are reported as form error. 3. In case of a CRC Error and a CRC delimiter corruption, only the FMER bit is set. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 21 • 1 = Indicates that the core is either receiving a message BBSY or transmitting a message. • 0 = Indicates that the core is either in Configuration mode or the bus is idle. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 22 This bit can be cleared by writing to the respective bit in the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 23 TX Cancellation Request Served Interrupt. TXCRS • 1 = Indicates that a cancellation request was cleared. This bit can be cleared by writing to the respective bit in the ICR. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 24 This bit can be cleared by writing to the respective bit in the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 25 RX Match Not Finished interrupt Enable. ERXMNF • 1 = Enables interrupt generation if RXMNF bit in the ISR is set. • 0 = Disables interrupt generation if RXMNF bit in the ISR is set. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 26 RX FIFO-0 Overflow Interrupt Enable (Sequential/FIFO Mode). ERFXOFLW • 1 = Enables interrupt generation if RFXOFLW bit in the ISR is set. • 0 = Disables interrupt generation if RFXOFLW bit in the ISR is set. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 27 • 1 = Clears RX FIFO-1 Watermark Full interrupt status bit CRXFWMFLL_1 (Sequential/FIFO Mode). Writing a 1 to this bit clears the respective bit in the ISR. Reads always 0. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 28 Writing a 1 to this bit clears the respective bit in the ISR. Reads always 0. • 1 = Clears Bus-Off Recovery Done interrupt status bit. CBSFRD Writing a 1 to this bit clears the respective bit in the ISR. Reads always 0. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 29 • 1 = Enables TDC function as specified in the CAN FD standard. • 0 = TDC is disabled. This bit can be written only when CEN bit in SRR is 0. 15:14 Reserved – Reserved CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 30 Data Bit Timing. 11:8 DP_TS2[3:0] The actual value is one more than the value written to the register. This bit can be written only when CEN bit in SRR is 0. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 31 In those situation, buffer scheduler trigger is postponed till the event is over). Unnecessary writes to this register might reduce core throughput on the CAN bus. Ensure IMPORTANT: this register is written only when it is required. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 32 If internal buffer scheduling round is in progress, then Note: cancellation consideration is postponed till it is over. Notes: 1. Host can set cancellation requests for multiple buffers in one write to this register. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 33 If FILL level is 0, setting this bit has no effect. The FILL level might remain unchanged when IRI is written if core is just finishing a successful transmission and incrementing internal write index. This bit always read as 0. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 34 TX Event FIFO Fill Level is above TX Event FIFO Full watermark. This field can be written to only when CEN bit in SRR is 0. 31:5 Reserved Reserved. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 35 Table 2-24, page This register space is reserved for RX Sequential/FIFO mode or when number of RX mailbox Note: buffers are 16. When reserved, write has no effect and read returns 0. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 36 Table 2-26: Interrupt Enable RX Buffer Full Register 1 Default Bits Name Access Description Value 31:16 Reserved – Reserved RX Buffer_47/33 Full Interrupt Enable 15:1 ERBF47/ERBF33 Description same as ERBF32. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 37 Use Acceptance Filter Mask Pair 29. UAF29 Description same as UAF0. Use Acceptance Filter Mask Pair 28. UAF28 Description same as UAF0. Use Acceptance Filter Mask Pair 27. UAF27 Description same as UAF0. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 38 Use Acceptance Filter Mask Pair 10. UAF10 Description same as UAF0. Use Acceptance Filter Mask Pair 9. UAF9 Description same as UAF0. Use Acceptance Filter Mask Pair 8. UAF8 Description same as UAF0. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 39 For example, if FL = 0x5 and RI = 0x2 then RX FIFO-1 has five messages starting from Read Index 2 (Start address 0x4190). FL is maintained if CEN bit is cleared. FL gets reset to 0 if soft or hard reset is asserted. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 40 If FILL level is 0, setting this bit has no effect. The FILL level might remain unchanged when IRI is written if core is just finishing a successful receive and incrementing internal write index. This bit always read as 0. Reserved – Reserved. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 41 RX FIFO-1 Fill Level is above RX FIFO-1 Full watermark. This field can be written to only when CEN bit in SRR is 0. Reserved – Reserved. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 42 TB DW0 Register 0x012C TB0-DW9 Read, Write 0x0130 TB0-DW10 Read, Write 0x0134 TB0-DW11 Read, Write 0x0138 TB0-DW12 Read, Write 0x013C TB0-DW13 Read, Write 0x0140 TB0-DW14 Read, Write 0x0144 TB0-DW15 Read, Write CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 43 0x0460- access to this address space TB12 Read, Write 0x04A4 and read access returns 0. 0x04A8- TB13 Read, Write 0x04EC 0x04F0- TB14 Read, Write 0x0534 0x0538- TB15 Read, Write 0x057C CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 44 0x09B8- TB31 Read, Write 0x09FC 32 ID Filter-Mask Pairs 0x0A00 M0/AFMR0 Read, Write Acceptance Filter Mask Register ID Filter Mask pair 0 0x0A04 F0/AFIR0 Read, Write Acceptance Filter ID Registers CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 45 Valid for both CAN and CAN FD Standard and Extended Control Frames. • 1 = Indicates the use of an Extended Message Identifier. • 0 = Indicates the use of a Standard Message Identifier. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 46 BRS does not exist in CAN format frames and should be set Note: to 0. Reserved Reserved. Write to this field should be 0. Event FIFO Control. Control • 0 = Don't store TX events. • 1 = Store TX Events. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 47 TXE FIFO TB0-ID Read Only TXE FIFO TB ID Register 0x2004 TXE FIFO TB0-DLC Read Only TXE FIFO TB DLC Register 0x2008 TXE FIFO TB1-ID Read Only TXE FIFO TB ID Register CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 48 Valid for both CAN and CAN FD Standard and Extended Status Frames. • 1 = Indicates the use of an Extended Message Identifier. • 0 = Indicates the use of a Standard Message Identifier. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 49 Data phase inside a CAN FD frame • 0 = Bit rate is not switched inside a CAN FD frame. BRS does not exist in CAN format frames and should be set Note: to 0. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 50 Host interface to RX block RAM message space (core does not block writes to 0x2108 RB0-DW0 Read Only RB DW0 Register RX block RAM message space). CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 51 1. Read from uninitialized memory location might return X or invalid data. Asserting a soft or hard reset does not clear block RAM locations. 2. Message Buffer element resides in RX block RAM. Host should respect read access rules to avoid memory collisions. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 52 RB DW0 Register space). 0x412C RB0_1-DW9 Read Only 0x4130 RB0_1-DW10 Read Only 0x4134 RB0_1-DW11 Read Only 0x4138 RB0_1-DW12 Read Only 0x413C RB0_1-DW13 Read Only 0x4140 RB0_1-DW14 Read Only 0x4144 RB0_1-DW15 Read Only CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 53 CAN remote frames as following • 1 = Indicates that the received message is a Standard Remote CAN Frame. • 0 = Indicates that the received message is a Standard Data CAN Frame. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 54 This bit distinguishes between CAN format and CAN FD format frames. EDL/FDF Status • 1 = Received frame is a CAN FD format frame. • 0 = Received frame is a CAN format frame. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 55 Data byte that was received with CAN or CAN FD frame based on DLC control field. Data Byte 2. 15:8 Data bytes2 [7:0] Data byte that was received with CAN or CAN FD frame based on DLC control field. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 56 RX FIFO-1. In this case, the RXFP field should be less than 'd31. The incoming Identifier is masked with the bits in the Acceptance Filter Mask register. 6. The Acceptance Filter ID register is also masked with the bits in the Acceptance Filter Mask register. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 57 RX FIFO 0 RX FIFO 1 FPj = Filter Mask Pair (j = 0,1...31) Receive Filter Partition (RXFP) = i X21312-081618 X21311-081518 X21311-081518 X21310-081518 Figure 2-2: Normal Operation (RX FIFO-1) CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 58 All bit fields (AMID[28:18], AMSRR, AMIDE, AMID[17:0], and AMRTR) need to be defined for Extended frames. Only AMID[28:18], AMSRR, and AMIDE need to be defined for Standard frames. AMID[17:0] and AMRTR should be written as 0 for Standard frames. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 59 The Acceptance Filter ID registers (AFIR) contain Identifier bits, which are used for acceptance filtering. All bit fields (AIID[28:18], AISRR, AIIDE, AIID[17:0], and AIRTR) need to be defined for Extended frames. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 60 0x212C RB0-DW9 Read, Write RAM locations). 0x2130 RB0-DW10 Read, Write 0x2134 RB0-DW11 Read, Write 0x2138 RB0-DW12 Read, Write 0x213C RB0-DW13 Read, Write 0x2140 RB0-DW14 Read, Write 0x2144 RB0-DW15 Read, Write CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 61 = 16 or 32. In this RB33 Read, Write 0x2A8C case, core does not allow any write access to this address space and read access returns 0. 0x2E38- RB47 Read, Write 0x2E7C CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 62 RB*-DW Register (Address Offset + 0x2108, 0x210C,…0x2150, 0x2154, …0x4108,...) Description same as listed in Table 2-41, page MRB* Register (Address Offset + 0x2F00, 0x2F04,…) Description same as listed in Table 2-42, page CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 63: Chapter 3: Designing With The Core

    Protocol Exception (PEE) state • Bus-Off Recovery State Figure 3-1 shows the core operating mode transitions and Table 3-1 defines the modes of operation with corresponding control and status bits. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 64 Bits (Hard) Operation Mode Reset SRST BSFR_ PEE_ CEN LBACK SLEEP SNOOP Config LBACK SLEEP NORMAL SNOOP Config Config Reset) Core is under reset (reset) Core is under reset (reset) CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 65 Driving a 0 on the Reset input. After reset, the core exits Configuration mode after the CEN bit is set and 11 consecutive nominal recessive bits are seen on the CAN bus. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 66 Configuration mode. • CAN FD enters Normal, Loopback, Snoop or Sleep modes from Configuration mode, depending on the LBACK, SNOOP, and SLEEP bits in the MSR Register. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 67: Normal Mode

    Whenever the SLEEP bit is 1, and bus activity is detected. • Whenever there is a new message for transmission. Interrupts are generated when the core enters Sleep mode or wakes up from Sleep mode. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 68: Programming Model

    Stores received messages based on programmed ID filtering. • Error counters are disabled and cleared to 0. Reads to the Error Counter Register to return 0. Xilinx recommends that Snoop mode is programmed only after system reset or RECOMMENDED: software reset. Protocol Exception State The CAN FD enters CAN FD Protocol Exception (PEE) state if it receives the res bit to be recessive in the CAN FD frame (provided the DPEE bit is not set in the MSR register).
  • Page 69 Write 1 to the UAF bit corresponding to the Acceptance Filter Mask and ID register ° pair. Repeat the steps for each Acceptance Filter Mask and ID register pair. ° CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 70 After the occurrence of 11 consecutive recessive bits, the CAN FD clears the CONFIG bit in the Status register to 0 and sets the appropriate Mode Status bit in the Status register. If the CEN bit is cleared during core operation, Xilinx recommends resetting the core RECOMMENDED: so that operation starts afresh.
  • Page 71 If there is already a pending cancellation request for TXB_i, no action is required and the Host should wait (by poll/interrupt) until the core serves a cancellation request for TXB_i. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 72 3. New message availability can be found by polling FSR register or by Watermark Full interrupts indication. 4. Read a new message (from RX FIFO-0 or RX FIFO-1) starting from its respective Read Index location (given in FSR register field). CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 73 1. The incoming Identifier is masked with the bits in the Acceptance Filter Mask register. 2. The Filter ID register is also masked with the bits in the Acceptance Filter Mask register. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 74 Full). Together, these two bits give the buffer status as Inactive, Active, Full, or Invalid. These bits are described in detail in the Receive Buffer Control Status (RCS) registers. Each receive message element also has one ID Mask Register in the RX block RAM. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 75 Full buffer, the overflow condition is generated and the matching buffer index is captured in the ISR. When there is also no match in the full buffers, the message is discarded without indication. CAN FD v2.0 Send Feedback PG223 December 5, 2018...
  • Page 76 5. The ID received with the message is written into the ID field of the Mailbox buffer. Example 1: Host programmed ID & Mask: ID reg : 0x1234_5678 Mask reg : 0xFFFF_FF00 Incoming IDs 0x1234_56xx will match this mailbox buffer. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 77: Clocking

    The Transfer layer remains in reset as long as the CEN (CAN enable) bit in the SRR register is 0 (that is, the CEN bit is the third source of reset for the Transfer layer). If the CEN bit is CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 78: Interrupts

    Chapter 3: Designing with the Core cleared during core operation, Xilinx recommends resetting the core so that operation starts over. The Object layer is reset synchronously with respect to the above mentioned two sources (that is, internal reset assertion and deassertion to Object layer is done synchronous to AXI4-Lite/APB clock).
  • Page 79 Changing an IER bit from 1 to 0 when the corresponding bit in the ISR is 1. When both deassertion and assertion conditions occur simultaneously, the interrupt line is deasserted first, and is reasserted if the assert condition remains TRUE. CAN FD v2.0 Send Feedback PG223 December 5, 2018...

  • Page 80: Chapter 4: Design Flow Steps

    [Ref 10] Customizing and Generating the Core ® This section includes information about using Xilinx tools to customize and generate the core in the Vivado Design Suite. If you are customizing and generating the core in the IP integrator, see the Vivado Design...
  • Page 81 IP instance. Valid values are 8, 16, and 32. • RX Mode – This parameter decides the message reception mode used in the current IP instance. Valid values are as follows: CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 82 RX MailBox mode. RX FIFO-0 Depth C_RX_FIFO_0_DEPTH This parameter is valid only Note: Valid values are 32 and 64. Valid values are 32 and 64. when the IP is in FIFO/Sequential mode. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 83: Constraining The Core

    AXI4 clock is required to run at a higher frequency. • The CAN clock frequency can be 8 to 80 MHz. • The AXI4 clock frequency can be 8 to 200 MHz. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 84: Simulation

    For cores targeting 7 series or Zynq-7000 SoC devices, UNIFAST libraries are not IMPORTANT: supported. Xilinx IP is tested and qualified with UNISIM libraries only. Synthesis and Implementation For details about synthesis and implementation, see the Vivado Design Suite User Guide:...

  • Page 85: Chapter 5: Example Design

    DUT and PARTNER to program and to check the status. • CAN FD Partner – The CAN FD IP in default mode to transmit and receive the packets to and from DUT. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 86: Simulating The Example Design

    The Software Reset register is written to enable the CEN bit, which enables the DUT and Partner. • Writes two packets into DUT TX buffers (one CAN and one CAN FD). This demonstrates the transmission packet priority in the core. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 87 If DUT is configured in Mailbox mode, the packets are read from buffers enabled and compared for correct reception. CAN FD frames are transmitted with a dual bit rate. Note: CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 88 200 MHz clock and drives an initial reset to the example design. X-Ref Target - Figure 6-1 <component_name>_tb clk_in1_p clk_in1_n Clock Reset Generation reset Example Design done Test Status Checker status X14809-081418 Figure 6-1: Test Bench CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 89: Compliance Testing

    References, page If any of the listed requirements are not met, various frame errors can be seen when performing the CAN FD communication. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 90: Upgrading In The Vivado Design Suite

    Port Descriptions for details. apb_psel Port Descriptions for details. apb_penable Port Descriptions for details. Port Descriptions for details. apb_prdata[31:0] apb_pready Port Descriptions for details. apb_perror Port Descriptions for details. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 91: Finding Help On Xilinx.com

    Answer Records Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available.

  • Page 92: Technical Support

    Xilinx provides technical support at the Xilinx Support web page for this LogiCORE™ IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support if you do any of the following: • Implement the solution in devices that are not defined in the documentation.

  • Page 93: Debug Tools

    Captured signals can then be analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx devices. The Vivado logic analyzer is used with the logic debug LogiCORE IP cores, including: •...

  • Page 94: Interface Debug

    Note: an example, and delays are not guaranteed to be the same as shown in the figure. X-Ref Target - Figure C-1 Figure C-1: AXI4-Lite Interface Read Timing Diagram CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...
  • Page 95 The main core clocks are toggling and that the enables are also asserted. • If the simulation has been run, verify in simulation and/or in the Vivado Design Suite debug feature capture that the waveform is correct for accessing the AXI4-Lite interface. CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 96: Xilinx Resources

    Support. Documentation Navigator and Design Hubs Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): • From the Vivado® IDE, select Help > Documentation and Tutorials.

  • Page 97: References

    10. Vivado Design Suite User Guide: Logic Simulation (UG900) 11. ISE to Vivado Design Suite Migration Guide (UG911) 12. Vivado Design Suite User Guide: Programming and Debugging (UG908) 13. Vivado Design Suite User Guide: Implementation (UG904) CAN FD v2.0 Send Feedback PG223 December 5, 2018 www.xilinx.com...

  • Page 98: Revision History

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

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