Uart Ch.n Transmit Data Register; Uart Ch.n Receive Data Register; Uart Ch.n Status And Interrupt Flag Register - Epson S1C17W22 Technical Manual

Bit 1 SFTRST
This bit issues software reset to the UART.
1 (W): Issue software reset
0 (W): Ineffective
1 (R): Software reset is executing.
0 (R): Software reset has finished. (During normal operation)
Setting this bit resets the UART transmit/receive control circuit and interrupt flags. This bit is auto-
matically cleared after the reset processing has finished.
Bit 0 MODEN
This bit enables the UART operations.
1 (R/W): Enable UART operations (The operating clock is supplied.)
0 (R/W): Disable UART operations (The operating clock is stopped.)
Note: If the UAnCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being
sent/received cannot be guaranteed. When setting the UAnCTL.MODEN bit to 1 again after
that, be sure to write 1 to the UAnCTL.SFTRST bit as well.

UART Ch.n Transmit Data Register

Register name Bit
UAnTXD 15–8 –
7–0 TXD[7:0]
Bits 15–8 Reserved
Bits 7–0 TXD[7:0]
Data can be written to the transmit data buffer through these bits. Make sure the UAnINTF.TBEIF bit
is set to 1 before writing data.

UART Ch.n Receive Data Register

Register name Bit
UAnRXD 15–8 –
7–0 RXD[7:0]
Bits 15–8 Reserved
Bits 7–0 RXD[7:0]
The receive data buffer can be read through these bits. The receive data buffer consists of a 2-byte
FIFO, and older received data is read first.

UART Ch.n Status and Interrupt Flag Register

Register name Bit
UAnINTF 15–10 –
9
8
7
6
5
4
3
2
1
0
Bits 15–10 Reserved
S1C17W22/W23 TECHNICAL MANUAL
(Rev. 1.3)
Bit name Initial
0x00
0x00
Bit name Initial
0x00
0x00
Bit name Initial
0x00
RBSY 0
TBSY 0
– 0
TENDIF 0
FEIF 0
PEIF 0
OEIF 0
RB2FIF 0
RB1FIF 0
TBEIF 1
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
Reset R/W
– R –
H0 R
Reset R/W
– R –
H0/S0 R
H0/S0 R
– R
H0/S0 R/W Cleared by writing 1.
H0/S0 R/W Cleared by writing 1 or reading the
UAnRXD register.
H0/S0 R/W
H0/S0 R/W Cleared by writing 1.
H0/S0 R Cleared by reading the UAnRXD reg-
ister.
H0/S0 R
H0/S0 R Cleared by writing to the UAnTXD
register.
12 UART (UART)
Remarks
Remarks
Remarks
12-11