Uart3 Ch.n Control Register; Uart3 Ch.n Transmit Data Register; Uart3 Ch.n Receive Data Register - Epson S1C17M12 Technical Manual

11 UART (UART3)

UART3 Ch.n Control Register

Register name Bit
UAnCTL 15–8 –
7–2 –
1
0
Bits 15–2 Reserved
Bit 1 SFTRST
This bit issues software reset to the UART3.
1 (W): Issue software reset
0 (W): Ineffective
1 (R): Software reset is executing.
0 (R): Software reset has finished. (During normal operation)
Setting this bit resets the UART3 transmit/receive control circuit and interrupt flags. This bit is auto-
matically cleared after the reset processing has finished.
Bit 0 MODEN
This bit enables the UART3 operations.
1 (R/W): Enable UART3 operations (The operating clock is supplied.)
0 (R/W): Disable UART3 operations (The operating clock is stopped.)
Note: If the UAnCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being
sent/received cannot be guaranteed. When setting the UAnCTL.MODEN bit to 1 again after
that, be sure to write 1 to the UAnCTL.SFTRST bit as well.

UART3 Ch.n Transmit Data Register

Register name Bit
UAnTXD 15–8 –
7–0 TXD[7:0]
Bits 15–8 Reserved
Bits 7–0 TXD[7:0]
Data can be written to the transmit data buffer through these bits. Make sure the UAnINTF.TBEIF bit
is set to 1 before writing data.

UART3 Ch.n Receive Data Register

Register name Bit
UAnRXD 15–8 –
7–0 RXD[7:0]
Bits 15–8 Reserved
Bits 7–0 RXD[7:0]
The receive data buffer can be read through these bits. The receive data buffer consists of a 2-byte
FIFO, and older received data is read first.
11-12
Bit name Initial
0x00
0x00
SFTRST 0
MODEN 0
Bit name Initial
0x00
0x00
Bit name Initial
0x00
0x00
Seiko Epson Corporation
Reset R/W
– R –
– R
H0 R/W
H0 R/W
Reset R/W
– R –
H0 R/W
Reset R/W
– R –
H0 R
S1C17M12/M13 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 1.2)