Block Diagram - Xilinx ML405 User Manual

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Block Diagram

Figure 1-1
FLASH
FLASH
GPIO
(Pushbutton Switch/LED)
100 MHz XTAL + User
SMA
(Differential In/Out Clocks)
Dual PS/2
MGT: 2 Serial - ATA
MGT: 4 SMA
MGT: SFP
LVDS Clock Generators
for MGT Clocks
Figure 1-1: Virtex-4 ML405 Evaluation Platform Block Diagram
ML405 Evaluation Platform
UG210 (v1.5.1) March 10, 2008
shows a block diagram of the ML405 evaluation platform (board).
CF PC
Synchronous
SRAM
System ACE
Controller
32
Platform Flash
32
CPLD
32
Virtex-4
FPGA
I/O
Expansion Header
5V to USB and PS/2
TPS54610
6A SWIFT
TPS54610
6A SWIFT
5V Brick
6.5A
TPS54610
6A SWIFT
TPS73118
150 mA LDO
TPS73633
400 mA LDO
TPS54610
6A SWIFT
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Host
USB
Peripheral
Controller
Peripheral
10/100/1000
Ethernet PHY
DDR SDRAM
DDR SDRAM
Audio CODEC
16 32
RS-232 XCVR
Character LCD
User IIC Bus
IIC EEPROM
TPS51100
3A DDR LDO
2.5V
2.5V to DDR SDRAM
UC385
1.5V (Digital)
5A Linear
MAX8556/7
3.3V
4A Linear
to FPGA I/O
1.8V
to PROM
3.3V
to VGA DAC
1.2V
to FPGA Core
Introduction
RJ-45
Line Out/
Headphone
AC97
Mic In /
Line In
Video
VGA
Serial
16 X 32
1.25V
to VTT
1.5V (Analog)
to FPGA MGTs
1.2V
to FPGA MGTs
1.5V (Digital)
UG210_01_061606
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