Block Diagram; Related Xilinx Documents - Xilinx ML505 User Manual

Chapter 1: ML505/ML506/ML507 Evaluation Platform

Block Diagram

CPLD
Misc. Glue Logic
GPIO
(Button/LED/DIP Switch)
Piezo/Speaker
PLL Clock Generator
Plus User Oscillator
System Monitor
SMA
(Differential In/Out Clocks)
Dual PS/2
GTP: 2 Serial ATA
GTP: 4 SMA
GTP: 4 SFP
GTP: PCIe 1x

Related Xilinx Documents

14
Downloaded from Elcodis.com electronic components distributor
Figure 1-1 shows a block diagram of the ML50x Evaluation Platform (board).
Sync
SRAM
32
16
Flash
SPI
16
32
Figure 1-1: Virtex-5 FPGA ML50x Evaluation Platform Block Diagram
Prior to using the ML50x Evaluation Platform, users should be familiar with Xilinx
resources. See Appendix C, "References"
following locations for additional documentation on Xilinx tools and solutions:
•
EDK: www.xilinx.com/edk
•
ISE: www.xilinx.com/ise
•
Answer Browser:
•
Intellectual Property:
CF PC4
System ACE
Controller
Platform Flash
16 32
Virtex-5
LXT/SXT/FXT
FPGA
User IIC Bus
XGI Header IIC EEPROM
for direct links to Xilinx documentation. See the
www.xilinx.com/support
www.xilinx.com/ipcenter
www.xilinx.com
Host
USB
Peripheral
Controller
Peripheral
10/100/1000
RJ-45
Ethernet PHY
DDR2
SO-DIMM
Digital Audio
AC97
Line Out /
Audio CODEC
Headphone
Mic In / Line In
VGA Input
Codec
DVI Output
DVI-I Video Out
Codec
Serial
RS-232 XCVR
Battery and
Fan Header
16 X 32
Character LCD
UG347_03_110807
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
R