Block Diagram; Related Xilinx Documents - Xilinx ML605 Hardware User's Manual
Hide thumbs
Also See for ML605:
- User manual (92 pages) ,
- Hardware tutorial (40 pages) ,
- Manual (22 pages)
Table of Contents
Advertisement
Chapter 1:
ML605 Evaluation Board
Block Diagram
Figure 1-1
X-Ref Target - Figure 1-1
System ACE CF
S.A. CompactFlash
S.A. 8-bit MPU I/F
Platform Flash
Linear BPI Flash
DVI Codec
VGA Video
DVI Video Connector
10/100/1000
Ethernet PHY
MII/GMII/RMII
SODIMM Socket
204-pin, DDR3
Decoupling Caps
User LED/SW
MEM Vterm
User DIP SW
Regulator
User LCD
Related Xilinx Documents
Prior to using the ML605 Evaluation Board, users should be familiar with Xilinx resources.
See
locations for additional documentation on Xilinx tools and solutions:
•
•
•
•
12
Send Feedback
shows a high-level block diagram of the ML605 and its peripherals.
JTAG USB Mini-B
USB JTAG Circuit
BANK32
BANK24
BANK34
BANK32
XC6VLX240T - 1FFG1156
BANK33
BANK 25, 35
BANK 26, 36
BANK14, 33, 36
BANK24,34
200 MHz LVDS Clock
SMA Clock
User S.E. 2.5V Clock
Figure 1-1: ML605 High-Level Block Diagram
Appendix E, References
for a direct link to Xilinx documentation. See the following
ISE:
www.xilinx.com/ise
Embedded Development Kit:
Intellectual Property:
www.xilinx.com/ipcenter
Answer Browser:
www.xilinx.com/support
www.xilinx.com
VITA 57.1 FMC
HPC Connector
BANK12, 13
BANK15,16
BANK14,22
BANK34,116
BANK23,24
BANK112,113
BANK0
BANK33
BANK34
Virtex-6
FPGA
BANK116
BANK114
BANK115
BANK14
BANK24
USB Controller
CP2103 USB-TO-UART
Host Type "A"
Peripheral Mini-B
Connectors
www.xilinx.com/edk
VITA 57.1 FMC
LPC Connector
SYSMON I/F
INIT, DONE LEDs
PROG PB, MODE SW
IIC Bus
IIC EEPROM
FMC HPC
DDR3 SODIMM IIC
FMC LPC
SFP Module
Connector
SGMII
PCIe X8 Edge Connector
MGT SMA REF Clock
MGT RX/TX SMA Port
Bridge
USB Mini-B
UG534_01_092709
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
Advertisement
Table of Contents
