Block Diagram - Xilinx ML50 Series User Manual

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Block Diagram

Figure 1-1
CPLD
Misc. Glue Logic
Flash
GPIO
(Button/LED/DIP Switch)
Piezo/Speaker
PLL Clock Generator
Plus User Oscillator
System Monitor
SMA
(Differential In/Out Clocks)
Dual PS/2
5V Brick
3A
Figure 1-1: Virtex-5 FPGA ML501 Evaluation Platform Block Diagram
ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
shows a block diagram of the ML501 Evaluation Platform (board).
CF
System ACE
Sync
Controller
SRAM
32
16
SPI Platform Flash
16
32
Virtex-5 LX
FPGA
XGI Header
PT Host 240W
10A Switching Regulator
PT Host 230W
6A Switching Regulator
PT Host 230W
6A Switching Regulator
www.xilinx.com
PC4
16 32
User IIC Bus
IIC EEPROM
5V
To USB and PS/2
1.0V
To FPGA Core
2.5V
TPS74401
3.3V
3A LDO
To V
2.5V
TPS74401
3A LDO
To FPGA I/O
To FPGA I/O
1.8V
To PROM
To DDR2 SO-DIMM
0.9V
TPS51100
3A LDO
To V
0.9V
TPS51100
3A LDO
To V
Introduction
Host
USB
Peripheral
Controller
Peripheral
10/100/1000
RJ-45
Ethernet PHY
DDR2
SO-DIMM
Digital Audio
AC97
Line Out /
Audio CODEC
Headphone
Mic In / Line In
Video DAC DVI-I Video Out
RS-232 XCVR Serial
Battery and
Fan Header
16 X 32
Character LCD
CCAUX
TTVREF
TT
UG226_03_083006
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