Block Diagram - Xilinx SP605 Hardware User's Manual

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Block Diagram

The following figure shows a high-level block diagram of the SP605 and its peripherals.
X-Ref Target - Figure 1-1
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
17. Switches
• Power On/Off slide switch
• System ACE CF Reset pushbutton
• System ACE CF bitstream image select DIP switch
• Mode DIP switch
18. VITA 57.1 FMC LPC Connector
19. Power Management
• AC Adapter and 12V Input Power Jack/Switch
• Onboard Power Regulation
Configuration Options
• 3. SPI x4 Flash (both onboard and off-board)
• 4. Linear BPI Flash
• 5. System ACE CF and CompactFlash Connector
• 6. USB JTAG
1-Lane I/Fs:
LED
PCIe Edge Conn.
DIP Switch
SMA x4 SFP
User SMA x2
FMC-LPC
JTAG JTAG
System ACE
MPU I/F
L/S
JTAG
USB JTAG Logic
and USB Mini-B
Connector
DDR3
Component
Memory
L/S
Pushbuttons
DIP Switch
GPIO Header
LED,
DIP Switch
= Level Shifter
L/S
Figure 1-1: SP605 Features and Banking
www.xilinx.com
PCIe 125 MHz Clk
SMA REFCLK
SFPCLK
FMC GBTCLK
DED
MGTs
Bank 0
2.5V
Spartan-6
Bank 3 Bank 1
XC6SLX45T-3FGG484
1.5V
U1
Bank 2
2.5V
SPI x4, Part of FMC-LPC
SPI Header Expansion Conn.
Overview
Part of
FMC-LPC
SFP IIC Bus
Expansion
Connector
Main IIC Bus
USB UART and
USB Mini-B
Connector
DVI Codec and
2.5V
DVI Connector
10/100/1000
Ethernet PHY,
Status LEDs,
and Connector
Parallel Flash
DVI IIC Bus
UG526_01_110409
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