Block Diagram - Xilinx VCK190 Series User Manual

Block Diagram

The VCK190 block diagram is shown in the following figure.
HDMI
HSDP
2x zSFP
Lane 4
Lane 5
Lane 6
PCIe
Lane 7
GEN4
x8
Lane 0
Lane 1
Lane 2
Lane 3
MIO
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Figure 2: Block Diagram
SysC, GPIO
1.8V
GTY0
HDIO
GTY
GTY1
GTY2
GTY3
Bank 106
GTY0
GTY
GTY1
GTY2
GTY3
Bank 105
GTY0
GTY
GTY1
GTY2
GTY3
Bank 104
GTY0
GTY
GTY1
GTY2
GTY3
Bank 103
Versal VC1902
VSVA2197
CPM
PMC_MI0[0:25] Bank 500
PMC_MI0[26:51] Bank 501
LP_MI0[0:25] Bank 502
XPIO XPIO
Triplet 1 Triplet 2
700 701 702 703 704
DDR4 72-bit LPDDR4
UDIMM 2x (1x32)
HDMI, PCIe
3.3V
HDIO
MRMAC
MRMAC
MRMAC
MRMAC
XPIO
Triplet 3
705 706 707 708 709
2x (1x32)
FMC+_01 FMC+_02
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Chapter 1: Introduction
GTY0
4
GTY
GTY1
GTY2
GTY3
Bank 206
GTY0
GTY 4
GTY1
GTY2
GTY3
Bank 205
GTY0
4
GTY
GTY1
GTY2
GTY3
Bank 204
GTY0
4
GTY
GTY1
GTY2
GTY3
Bank 203
GTY0
4
GTY
GTY1
GTY2
GTY3
Bank 202
GTY0
4
GTY
GTY1
GTY2
GTY3
Bank 201
GTY0
4
GTY
zQSFP
GTY1
GTY2
GTY3
Bank 200
XPIO
Triplet 4
710 711
LPDDR4
12
12
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