Quad Spi Flash Memory (Mio 0-12); Gpio (Mio 13, 38) - Xilinx ZCU111 User Manual

Quad SPI Flash Memory (MIO 0–12)
[Figure 2-1, callout 4]
The Micron dual MT25QU02GCBB8E12-0sit serial NOR flash Quad SPI flash memory can
hold the boot image for the RFSoC system. This interface is used to support QSPI32 boot
mode as defined in the Zynq UltraScale+ Device Technical Reference Manual (UG1085)
[Ref 3].
The dual Quad SPI flash memory located at U17/U18 provides 4 Gb of non-volatile storage
that can be used for configuration and data storage.
• Part number: MT25QU02GCBB8E12-0SIT (Micron)
• Supply voltage: 1.8V
• Datapath width: 8 bits
• Data rate: various depending on single, dual, or quad mode
The configuration and Quad SPI flash memory section of the Zynq UltraScale+ Device
Technical Reference Manual (UG1085)
more Quad SPI details, see the Micron MT25QU02GCBB8E12-0SIT data sheet at the Micron
website [Ref 15].
The connections between the Quad SPI flash memory and XCZU28DR PS bank 500 are
referenced in Appendix B, Xilinx Design

GPIO (MIO 13, 38)

These two GPIO bits are connected to the U42 MSP430 system controller for general
purpose signaling or communications between the Zynq UltraScale+ RFSoC device and the
MSP430 system controller. These signals are level-shifted by TSX0108E U41. The
connections between the U42 system controller and the XCZU28DR RFSoC are listed in
Table 3-3.
Table 3-3: System Controller U42 GPIO Connections to XCZU28DR U1
XCZU28DR (U1)
Pin
E27
R28
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
[Ref 3]
Constraints.
Net Name
MIO38_PS_GPIO1
MIO13_PS_GPIO2
www.xilinx.com
Chapter 3: Board Component Descriptions
provides details on using the memory. For
MSP430 U42
Pin Name Pin #
P1_6 19
P1_7 20
27
Send Feedback