Ddr4 Component Memory; Ddr4 Memory 80-Bit I/F C1 To Fpga U1 Banks 71, 72, And 73 - Xilinx VCU118 User Manual

DDR4 Component Memory

[Figure 2-1, callout 4]
The 2.5 GB DDR4 component memory system is comprised of two sets of five 256 Mb x 16
(80-bit wide) DDR4 SDRAM devices (Micron MT40A256M16GE-075E) located at U60-U64
(C1) and U135-U139 (C2). This dual memory system is connected in 80-bit wide interfaces
to the U1 XCVU9P HP banks 71, 72, 73 (C1) and 40, 41, 42 (C2). The DDR4 0.6V VTT
termination voltages (nets DDR4_C1_VTT and DDR4_C2_VTT) are sourced from the TI
TPS51200DR linear regulators U24 and U134. The DDR4 memory interface bank VREF pins
are not connected, which, coupled with an XDC set_property INTERNAL_VREF constraint,
invoke the INTERNAL VREF mode. The connections between the C1 80-bit interface DDR4
component memories and XCVU9P banks 71, 72, and 73 are listed in
Table 3-2: DDR4 Memory 80-bit I/F C1 to FPGA U1 Banks 71, 72, and 73
FPGA (U1)
Schematic Net Name
Pin
F11 DDR4_C1_DQ0
E11 DDR4_C1_DQ1
F10 DDR4_C1_DQ2
F9 DDR4_C1_DQ3
H12 DDR4_C1_DQ4
G12 DDR4_C1_DQ5
E9 DDR4_C1_DQ6
D9 DDR4_C1_DQ7
R19 DDR4_C1_DQ8
P19 DDR4_C1_DQ9
M18 DDR4_C1_DQ10
M17 DDR4_C1_DQ11
N19 DDR4_C1_DQ12
N18 DDR4_C1_DQ13
N17 DDR4_C1_DQ14
M16 DDR4_C1_DQ15
D11 DDR4_C1_DQS0_T
D10 DDR4_C1_DQS0_C
P17 DDR4_C1_DQS1_T
P16 DDR4_C1_DQS1_C
G11 DDR4_C1_DM0
R18 DDR4_C1_DM1
L16 DDR4_C1_DQ16
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Standard
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
DIFF_POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
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Chapter 3: Board Component Descriptions
Table
Component Memory
Pin # Pin Name
G2 DQL0
F7 DQL1
H3 DQL2
H7 DQL3
H2 DQL4
H8 DQL5
J3 DQL6
J7 DQL7
A3 DQU0
B8 DQU1
C3 DQU2
C7 DQU3
C2 DQU4
C8 DQU5
D3 DQU6
D7 DQU7
G3 DQSL_T
F3 DQSL_C
B7 DQSU_T
A7 DQSU_C
E7 DML_B/DBIL_B
E2 DMU_B/DBIU_B
G2 DQL0
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3-2.
Ref. Des.
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U60
U61
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