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13 UART (UART2)
13.1 Overview
The UART2 is an asynchronous serial interface. The features of the UART2 are listed below.
• Includes a baud rate generator for generating the transfer clock.
• Supports 7- and 8-bit data length (LSB first).
• Odd parity, even parity, or non-parity mode is selectable.
• The start bit length is fixed at 1 bit.
• The stop bit length is selectable from 1 bit and 2 bits.
• Supports full-duplex communications.
• Includes a 2-byte receive data buffer and a 1-byte transmit data buffer.
• Includes an RZI modulator/demodulator circuit to support IrDA 1.0-compatible infrared communications.
• Can detect parity error, framing error, and overrun error.
• Can generate receive buffer full (1 byte/2 bytes), transmit buffer empty, end of transmission, parity error, framing
error, and overrun error interrupts.
• Can issue a DMA transfer request when a receive buffer
• Input pin can be pulled up with an internal resistor.
• The output pin is configurable as an open-drain output.
Figure 13.1.1 shows the UART2 configuration.
Item
Number of channels
Clock generator
CPU
DMA controller
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
Table 13.1.1 UART2 Channel Configuration of S1C31W74
UART2 Ch.n
CLK_UART2_n
CLKSRC[1:0]
CLKDIV[1:0]
DBRUN
MODEN
Receive data buffer
RXD[7:0]
Transmit data buffer
TXD[7:0]
TENDIE
FEIE
PEIE
OEIE
RB2FIE
RB1FIE
TBEIE
Figure 13.1.1 UART2 Configuration
Seiko Epson Corporation
byte full or a transmit buffer empty occurs.
one
S1C31W74
2 channels (Ch.0 and Ch.1)
Baud rate
BRT[7:0]
generator
FMD[3:0]
Transmit/receive
control circuit
SFTRST
Shift register
RZI demodulator
Shift register
RZI modulator
Interrupt
control circuit
DMA request
TBEDMAENx
RB1FDMAENx
control circuit
13 UART (UART2)
BRDIV
CHLN
PREN
PRMD
STPB
RBSY
TBSY
PUEN
USINn
INVRX
USOUTn
INVTX
IRMD
OUTMD
TENDIF
FEIF
PEIF
OEIF
RB2FIF
RB1FIF
TBEIF
13-1
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