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12 UART (UART)
• When the receive data buffer has a one-byte free space
The interrupt flag will be set when the first data byte already loaded is read out after the data
that encountered an error is transferred to the second byte entry of the receive data buffer.
12.6.2 Parity Error
If the parity function is enabled, a parity check is performed when data is received. The UART checks matching
between the data received in the shift register and its parity bit, and issues a parity error if the result is a non-match.
The received data that encountered an error is still transferred to the receive data buffer and the UAnINTF.PEIF
bit (parity error interrupt flag) is set to 1 when the data becomes ready to read from the UAnRXD register (see the
Note on framing error).
12.6.3 Overrun Error
If the receive data buffer is still full (two bytes of received data have not been read) when a data reception to the
shift register has completed, an overrun error occurs as the data cannot be transferred to the receive data buffer.
When an overrun error occurs, the UAnINTF.OEIF bit (overrun error interrupt flag) is set to 1.
12.7 Interrupts
The UART has a function to generate the interrupts shown in Table 12.7.1.
Interrupt
End of transmission
Framing error
Parity error
Overrun error
Receive buffer two bytes full UAnINTF.RB2FIF When the second received data byte is
Receive buffer one byte full UAnINTF.RB1FIF When the first received data byte is load-
Transmit buffer empty
The UART provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the
interrupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is
set. For more information on interrupt control, refer to the "Interrupt Controller" chapter.
12.8 Control Registers
UART Ch.n Clock Control Register
Register name
Bit
UAnCLK
15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
12-8
Table 12.7.1 UART Interrupt Function
Interrupt flag
UAnINTF.TENDIF When the UAnINTF.TBEIF bit = 1 after
the stop bit has been sent
UAnINTF.FEIF
Refer to the "Receive Errors."
UAnINTF.PEIF
Refer to the "Receive Errors."
UAnINTF.OEIF
Refer to the "Receive Errors."
loaded to the receive data buffer in which
the first byte is already received
ed to the emptied receive data buffer
UAnINTF.TBEIF
When transmit data written to the trans-
mit data buffer is transferred to the shift
register
Bit name
Initial
0x00
DBRUN
0
0x0
0x0
0x0
0x0
Seiko Epson Corporation
Set condition
Reset
R/W
–
R
–
H0
R/W
–
R
H0
R/W
–
R
H0
R/W
S1C17W22/W23 TECHNICAL MANUAL
Clear condition
Writing 1 or software reset
Writing 1, reading received
data that encountered an
error, or software reset
Writing 1, reading received
data that encountered an
error, or software reset
Writing 1 or software reset
Reading received data or
software reset
Reading data to empty
the receive data buffer or
software reset
Writing transmit data
Remarks
(Rev. 1.3)
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