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8
Watchdog Timer
8.1
Configuration of Watchdog Timer
The S1C63003/004/008/016 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1
as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software.
The watchdog timer must be reset cyclically by the software while it operates. If the watchdog timer is not reset in at
least 3–4 seconds, it generates a non-maskable interrupt (NMI) to the CPU.
Figure 8.1.1 is the block diagram of the watchdog timer.
OSC1 dividing signal 256 Hz
Watchdog timer enable signal
The watchdog timer contains a 10-bit binary counter, and generates the non-maskable interrupt when the last stage
of the counter (0.25 Hz) overflows.
Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when
the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic
processing takes place, just as for the timer interrupt routine.
The watchdog timer operates in the HALT mode. If a HALT status continues for 3–4 seconds, the non-maskable
interrupt releases the HALT status.
8.2
interrupt Function
If the watchdog timer is not reset periodically, the non-maskable interrupt (NMI) is generated to the core CPU. Since
this interrupt cannot be masked, it is accepted even in the interrupt disable status (I flag = "0"). However, it is not
accepted when the CPU is in the interrupt mask state until SP1 and SP2 are set as a pair, such as after initial reset or
during re-setting the stack pointer. The interrupt vector of NMI is assigned to 0100H in the program memory.
8.3
i/O Memory of Watchdog Timer
Table 8.3.1 shows the I/O address and control bits for the watchdog timer.
Address
Register name R/W Default
FF01H D3 0 (*3)
D2 0 (*3)
D1 WDen
R/W
D0 WDRST (*3)
*1 Initial value at initial reset
*4 Unused in the S1C63003/004/008
WDRST: Watchdog timer reset (FF01h•D0)
Resets the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading: Always "0"
When "1" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "0" is writ-
ten, no operation results. This bit is dedicated for writing, and is always "0" for reading.
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
Watchdog timer reset signal
Figure 8.
1.1 Watchdog timer block diagram
Table 8.
3.1 Control bits of watchdog timer
Setting/data
R
– (*2)
R
– (*2)
1
1 Enable
W
(Reset) 1 Reset
*2 Not set in the circuit
*5 Unused in the S1C63003/004
Seiko epson Corporation
Watchdog timer
–
Unused
–
Unused
0 Disable
Watchdog timer enable
0 Invalid
Watchdog timer reset (writing)
*3 Constantly "0" when being read
*6 Unused in the S1C63003
8 WaTChDOG TiMeR
Non-maskable
interrupt (NMI)
Function
8-1
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