Processor Status Register (Psr) - Epson S1C17 Series Manual

2 REGISTERS

2.3 Processor Status Register (PSR)

Symbol
PSR Processor Status Register
The Processor Status Register (hereinafter referred to as the "PSR") is an 8-bit register for storing the internal status
of the processor.
The PSR stores the internal status of the processor when the status has been changed by instruction execution. It is
referenced in arithmetic operations or branch instructions, and therefore constitutes an important internal status in
program composition. The PSR does not allow the program to directly alter its contents except for the IE bit.
As the PSR affects program execution, whenever an interrupt occurs, the PSR is saved to the stack, except for de-
bug interrupts, to maintain the PSR value. The IE flag (bit 4) in it is cleared to 0. The reti instruction is used to
return from interrupt handling, and the PSR value is restored from the stack at the same time.
IL[2:0] (bits 7–5): Interrupt Level
These bits indicate the priority levels of the processor interrupts. Maskable interrupt requests are accepted only
when their priority levels are higher than that set in the IL bit field. When an interrupt request is accepted, the
IL bit field is set to the priority level of that interrupt, and all interrupt requests generated thereafter with the
same or lower priority levels are masked, unless the IL bit field is set to a different level or the interrupt handler
routine is terminated by the reti instruction.
IE (bit 4): Interrupt Enable
This bit controls maskable external interrupts by accepting or disabling them. When IE bit = 1, the processor
enables maskable external interrupts. When IE bit = 0, the processor disables maskable external interrupts.
When an interrupt is accepted, the PSR is saved to the stack and this bit is cleared to 0. However, the PSR is not
saved to the stack for debug interrupts, nor is this bit cleared to 0.
C (bit 3): Carry
This bit indicates a carry or borrow. More specifically, this bit is set to 1 when, in an add or subtract instruction
in which the result of operation is handled as an unsigned 16-bit or 24-bit integer, the execution of the instruc-
tion resulted in exceeding the range of values representable by an unsigned 16-bit or 24-bit integer, or is reset to
0 when the result is within the range of said values.
Furthermore, the C flag will be set or reset by executing an shift instruction.
The C flag is set under the following conditions:
(1) When an addition executed by a 16-bit integer addition instruction (except a case of conditional execution)
results in a value greater than the maximum value 0xffff representable by an unsigned 16-bit integer
(2) When a subtraction executed by a 16-bit integer subtraction instruction (except a case of conditional execu-
tion) results in a value smaller than the minimum value 0x0000 representable by an unsigned 16-bit integer
(3) When a comparison (subtraction) executed by a 16-bit integer comparison instruction (except a case of con-
ditional execution) results in a value smaller than the minimum value 0x0000 representable by an unsigned
16-bit integer
(4) When a comparison (subtraction) executed by a 24-bit integer comparison instruction (except a case of
conditional execution) results in a value smaller than the minimum value 0x000000 representable by an un-
signed 24-bit integer
(5) When a shift operation of the register in which bit 0 is 1 is executed using a right logical shift instruction
(6) When a shift operation of the register in which bit 15 is 1 is executed using a left logical shift instruction
(7) When a shift operation of the register in which bit 0 is 1 is executed using a right arithmetic shift instruction
2-2
Register name
7 6 5
PSR IL[2:0]
Initial value 0 0 0
Figure 2.3.1 Processor Status Register (PSR)
Seiko Epson Corporation
Size R/W
8 bits R/W
4 3 2 1 0
IE C V Z N
0 0 0 0 0
Initial value
0x00
S1C17 CORE MANUAL
(REV. 1.2)