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7 Watchdog Timer (WDT)
7.1 Overview
WDT restarts the system if a problem occurs, such as when the program cannot be executed normally.
The features of WDT are listed below.
• Includes a 10-bit up counter to count reset generation cycle.
• A counter clock source and clock division ratio are selectable.
• Counter overflow generates a reset.
Figure 7.1.1 shows the configuration of WDT.
Clock generator
7.2 Clock Settings
7.2.1 WDT Operating Clock
When using WDT, the WDT operating clock CLK_WDT must be supplied to WDT from the clock generator.
The CLK_WDT supply should be controlled as in the procedure shown below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the "Power Supply,
Reset, and Clocks" chapter).
3. Set the following WDTCLK register bits:
WDTCLK.CLKSRC[1:0] bits
WDTCLK.CLKDIV[1:0] bits
4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
Use the following equation to calculate the WDT counter overflow cycle (reset generation cycle).
1,024
t
= — — — — — — — —
WDT
CLK_WDT
Where
t
:
Counter overflow cycle [second]
WDT
CLK_WDT: WDT operating clock frequency [Hz]
t
Example)
= 4 seconds when CLK_WDT = 256 Hz
WDT
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
WDT
WDTRUN[3:0]
WDTCNTRST
CLK_WDT
CLKSRC[1:0]
CLKDIV[1:0]
DBRUN
Figure 7.1.1 WDT Configuration
(Clock source selection)
(Clock division ratio selection = Clock frequency setting)
(Eq. 7.1)
Seiko Epson Corporation
7 WATCHDOG TIMER (WDT)
Reset
10-bit counter
request
7-1
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