Usi: Sending Slave Address And Transfer Direction Bit (Old) - Epson S1C33L26 Technical Manual

USI_CK pin (output)
USI_CK pin (input)
USI_DI pin (output)
USI_DI pin (input)
IMTGMOD[2:0] 0x0
IMTG (write)
IMBSY
IMSTA[2:0] 0x0
TD[7:0]
IMIF
Start interrupt
USI_CK pin (output)
USI_CK pin (input)
USI_DI pin (output)
USI_DI pin (input)
IMTGMOD[2:0]
IMTG (write)
IMBSY
IMSTA[2:0]
TD[7:0]
IMIF
* When IMIF is cleared via software, IMSTA[2:0] is also cleared to 0x0.
(1) Generating start condition
I C data transfer starts when the I
2
when the SCL line is maintained at high and the SDA line is pulled down to low.
To generate a start condition in this I
IMBSY is set to 1 while a start condition is being generated. When the start condition is generated, IMBSY
is reset to 0 and IMSTA[2:0] is set to 0x0. The I
Note: Other operations cannot be started before a start condition is generated.
(2) Sending slave address and transfer direction bit
After a start condition has been generated, send the address of the slave device to be communicated and a
transfer direction bit. I
buffer to send the slave address and transfer direction bit, enabling single transfers in 7-bit address mode. In
10-bit mode, data is sent twice or three times under software control. Figure 18.5.3.4 shows the configura-
tion of the address data.
S1C33L26 TECHNICAL MANUAL
A6 A5 A4 A3 A2 A1
0x2
*
Address
(1) Start condition → Data transmission
D7 D6 D5
ACK
0x6
0x5
* *
Receive
ACK interrupt
(2) Data transmission → Stop condition
2
Figure 18. 5.3.2 I C Master Data Transmission Timing Chart
C master device generates a start condition. The start condition applies
2
C master, set IMTGMOD[2:0] to 0x0 (default) and write 1 to IMTG.
2
SDA (USI_DI)
SCL (USI_CK)
Start condition
Figure 18. 5.3.3 Start Condition
2 C slave addresses are either 7-bit or 10-bit. This module uses an 8-bit transfer data
Seiko Epson Corporation
18 UNIVERSAL SERIAL INTERFACE (USI)
A0 R/W = 0 D7
ACK
0x6
0x2 0x5
* *
End of transmission Receive
interrupt ACK interrupt
D4 D3 D2 D1 D0
0x2
0x2
*
Transfer data n
End of transmission
interrupt
2 C bus is busy from this point on.
D6 D5 D4 D3 D2 D1
0x2
0x2
Transfer data 1
End of transmission
interrupt
ACK
0x6 0x1
0x5 0x1
* *
Receive Stop interrupt
ACK interrupt
D0
*
18-11