Agilent Technologies 4288A Programming Manual page 254

Status Reporting System
Status Register Structure
Table C-1 Status Bit Definitions of Status Byte (STB)
Issuing the *CLS command will clear all bits from the status byte register.
252
Bit
Name
Position
0 to 2 Not used
3 Questionable Status Register
Summary
4 MAV (Message Available)
5 Standard Event Status Register
Summary
6 RQS
7 Operation Status Register
Summary
Description
Always 0
Set to "1" when one of the enabled bits in the status event
status register is set to "1."
Set to "1" when the output queue contains data; reset to
"0" when all of the data has been retrieved.
Set to "1" when one of the enabled bits in the status event
status register is set to "1."
Set to "1" when any of the status byte register bits enabled
by the service request enable register is set to "1"; reset to
"0" when all of the data has been retrieved through serial
polling.
Set to "1" when one of the enabled bits in the operational
status register is set to "1."
Appendix C