Bus Timing Diagram - Motorola MC68824 User Manual

S4 S6 SO S2 S4 S6 S7
SO S2 S4 S6 S7 SO S2
CLK
IINPUT)
iiR
\ I
BG
\ I
BGACK
\
f'
AS
-.-l
\
f'
' \ {\
"---
I
OTHER
-+
FRONT·ENO
+-
TBC
-+
BACK·ENO
+
NEXT
~
BUS MASTER OVERHEAD CYCLE OVERHEAD BUS CYCLE
Figure 6-14. Bus Timing Diagram
6.5.2 Back-End Overhead
This overhead time is the delay between when the TBC has completed all operations and negated
AS, and the start of the next bus cycle which is controlled by another bus master. The TBC negates
the BGACK signal one cycle after the last bus cycle. One synchronization delay plus one-half clock
cycle later, the new bus master begins the next bus cycle.
6.6 REGISTERS
The following registers are user programmable: the command register (CR)' the data register
(DR), and the interrupt vector register (IV). Table 6-1 shows how the TBC registers are accessed
for 8-bit bus and Table 6-2 shows how the TBC registers are accessed using a 16-bit data bus.
Table 6-1. 8-Bit Bus Access
(CS=O and R/W=O)
A2
0
0
1
1
1
1
MOTOROLA
6-12
A1
0
1
0
0
1
1
AO
os
TBC Register
X 0 CR
X 0 IV
0 0 DR- Byte 3
1 0 DR - Byte 2
0 0 DR- Byte 1
1 0 DR- Byte 0
A2
0
0
1
1
1
1
1
1
Table 6-2. 16-Bit Bus Access
(CS=O and RIW=O)
A1
UOS
LOS
TBC Register
0
X
0 CR
1
X
0 IV
0 0 1
DR- Byte 3
0
1
0
DR - Byte 2
0 0 0 DR - High Word
1 0 1 DR - Byte 1
1 1 0 DR - Byte 0
1 0 0
DR- Low Word
MC68824 USER'S MANUAL