Table of Contents
Advertisement
VMEbus Accesses to the Local Bus
The VMEchip2 includes a user-programmable map decoder for the
VMEbus to local bus interface. The map decoder allows you to program
the starting and ending address and the modifiers the MVME172 responds
to.
VMEbus Short I/O Memory Map
The VMEchip2 includes a user-programmable map decoder for the GCSR.
The GCSR map decoder allows you to program the starting address of the
GCSR in the VMEbus short I/O space.
Software Support Considerations
The MVME172 is a complex board that interfaces to the VMEbus and
SCSI bus. These multiple bus interfaces raise the issue of cache coherency
and support of indivisible cycles. There are also many sources of bus error.
First, let us consider how interrupts are handled.
Interrupts
The MC68060 uses hardware-vectored interrupts.
Most interrupt sources are level and base vector programmable. Interrupt
vectors from the MC2 chip and the VMEchip2 have two sections, a base
value which can be set by the processor, usually the upper four bits, and
the lower bits which are set according to the particular interrupt source.
There is an onboard daisy chain of interrupt sources, with interrupts from
the MC2 chip having the highest priority, those from the IP2 chip having
the next highest priority, and interrupt sources from the VMEchip2 having
the lowest priority. Refer to Appendix A for an example of interrupt usage.
The MC2 chip, IP2 chip, and VMEchip2 ASICs are used to implement the
multilevel MC680x0 interrupt architecture. A PLD is used to combine the
individual IPLx signals from each ASIC.
http://www.mcg.mot.com/literature
Software Support Considerations
1
1-47
Advertisement
Table of Contents
