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Functional Description
to the VMEchip2 and Petra/MC2 descriptions in the MVME1X2P4 VME
Embedded Controller Programmer's Reference Guide for detailed
programming information.
Watchdog Timer
A watchdog timer function is provided in both the Petra/MC2 chip and the
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VMEchip2 ASIC. When the watchdog timer is enabled, it must be reset by
software within the programmed interval or it times out. The watchdog
timer can be programmed to generate a SYSRESET signal, a local reset
signal, or a board fail signal if it times out. Refer to the VMEchip2 and
Petra/MC2 descriptions in the MVME1X2P4 VME Embedded Controller
Programmer's Reference Guide for detailed programming information.
The watchdog timer logic is duplicated in the VMEchip2 and Petra/MC2
ASICs. Because the watchdog timer function in the VMEchip2 is a
superset of that function in the Petra/MC2 chip (system reset function), the
timer in the VMEchip2 is to be used in all cases except for versions of the
MVME172P4 which do not include the VMEbus interface (i.e., boards
ordered with a "No VMEbus Interface" option).
Software-Programmable Hardware Interrupts
The VMEchip2 ASIC supplies eight software-programmable hardware
interrupts. These interrupts allow software to create a hardware interrupt.
Refer to the VMEchip2 description in the MVME1X2P4 VME Embedded
Controller Programmer's Reference Guide for detailed programming
information.
Local Bus Timeout
The MVME172P4 provides timeout functions in the VMEchip2 ASIC and
the Petra/MC2 chip for the local bus. When the timer is enabled and a local
bus access times out, a Transfer Error Acknowledge (TEA) signal is sent
to the local bus master. The timeout value is selectable by software for 8
µsec, 64 µsec, 256 µsec, or infinity. The local bus timer does not operate
during VMEbus bound cycles. VMEbus bound cycles are timed by the
VMEbus access timer and the VMEbus global timer. Refer to the
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