Resets And Interrupts; Interrupt Sources - Motorola Semiconductor MC68HC11F1 Technical Manual

8-bit microcontroller

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5 Resets and Interrupts

There are three sources of reset on the MC68HC11F1 and MC68HC11FC0, each having its own reset

vector:

• RESET pin

• Clock monitor failure

• Computer operating properly (COP) failure

There are 22 interrupt sources serviced by 18 interrupt vectors. (The SCI interrupt vector services five

SCI interrupt sources.) Three of the interrupt vectors are non-maskable:

• Illegal opcode trap

• Software interrupt

• XIRQ pin (pseudo non-maskable interrupt)

The other 19 interrupts, generated mostly by on-chip peripheral systems, are maskable. Maskable in-

terrupts are recognized only if the global interrupt mask bit (I) in the condition code register (CCR) is

clear. Maskable interrupts have a default priority arrangement out of reset. However, any one interrupt

source can be elevated to the highest maskable priority position by writing to the HPRIO register. This

In addition to the global I bit, all maskable interrupt sources except the external interrupt (IRQ pin) are

subject to local enable bits in control registers. Each of these interrupt sources also sets a correspond-

ing flag bit in a control register that can be polled by software.

Several of these flags are automatically cleared during the normal course of responding to the interrupt

requests. For example, the RDRF flag is set when a byte has been received in the SCI. The normal

response to an RDRF interrupt request is to read the SCI status register to check for receive errors,

then to read the received data from the SCI data register. It is precisely these two steps that are required

to clear the RDRF flag, so no further instructions are necessary.

The following table summarizes the interrupt sources, vector addresses, masks, and flag bits.

MC68HC11F1/FC0

MC68HC11FTS/D

MOTOROLA

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