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Board Description and Memory Maps
1
Software Support Considerations
Interrupts
Cache Coherency
1-38
The MVME162FX is a complex board that interfaces to the VMEbus
and SCSI bus. These multiple bus interfaces raise the issue of cache
coherency and support of indivisible cycles. There are also many
sources of bus error. First, let us consider how interrupts are
handled.
The MC68040 uses hardware-vectored interrupts.
Most interrupt sources are level and base vector programmable.
Interrupt vectors from the MC2 chip and the VMEchip2 have two
sections, a base value which can be set by the processor, usually the
upper four bits, and the lower bits which are set according to the
particular interrupt source. There is an onboard daisy chain of
interrupt sources, with interrupts from the MC2 chip having the
highest priority, those from the IP2 chip having the next highest
priority, and interrupt sources from the VMEchip2 having the
lowest priority. Refer to Appendix A for an example of interrupt
usage.
The MC2 chip, IP2 chip, and VMEchip2 ASICs are used to
implement the multilevel MC680x0 interrupt architecture. A PLD is
used to combine the individual IPLx signals from each ASIC.
The MC68040 has the ability to watch local bus cycles executed by
other local bus masters such as the SCSI DMA controller, the LAN,
the VMEchip2 DMA controller, the VMEbus to local bus controller,
and the IP DMA controller.
When snooping is enabled, the MPU can source data and invalidate
cache entries as required by the current cycle. The MPU cannot
watch VMEbus cycles which do not access the local bus on the
MVME162FX. Software must ensure that data shared by multiple
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