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VMEchip2
2
DMAC Control Register 1 (bits 0-7)
ADR/SIZ
BIT
NAME
OPER
RESET
2-56
DHB
When this bit is high, the VMEbus has been acquired in
response to the DWB bit being set. When the DWB bit is
cleared, this bit is cleared.
ROBN
When this bit is high, the VMEbus arbiter operates in the
round robin mode. When this bit is low, the arbiter
operates in the priority mode.
7
6
DHALT
DEN
DTBL
S
S
R/W
0 PS
0 PS
0 PS
This control register is loaded by the processor; it is not modified when the
DMAC loads new values from the command packet.
DREQL
These bits define the VMEbus request level for the
DMAC requester. The request is only changed when the
VMEchip2 is bus master. The VMEchip2 always requests
at the old level until it becomes bus master and the new
level takes effect. If the VMEchip2 is bus master when the
level is changed, the new level does not take effect until
the bus has been released and re-requested at the old level.
The requester always requests the VMEbus at level 3 the
first time following a SYSRESET.
0
1
2
3
DRELM
These bits define the VMEbus release mode for the
DMAC requester. The DMAC always releases the bus
when the FIFO is full (VMEbus to local bus) or empty
(local bus to VMEbus).
0
1
2
$FFF40030 (8 bits of 32)
5
4
3
DFAIR
DRELM
R/W
R/W
0 PS
0 PS
VMEbus request level 0
VMEbus request level 1
VMEbus request level 2
VMEbus request level 3
Release when the time on timer has expired
and a BRx* signal is active on the VMEbus.
Release when the time on timer has expired.
Release when a BRx* signal is active on the
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2
1
0
DREQL
R/W
0 PS
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