Appendix 4.6 Transmission Delay Time Of Master Station <-> Local Station; (Ver.2 Compatible Device Station) - Mitsubishi Electric L26CPU-BT User Manual

Appendix 4.6
(1) Master station (RX)  Local station (RY), Master station (RWr)  Local station
(RWw)
This indicates the time from the moment a local station CPU device turns ON (OFF) until the corresponding
master station CPU device turns ON (OFF).
Or, it indicates the time from when data is set to a local station CPU device until the data is stored to the
corresponding master station CPU device.
(a) Expression
The meanings of symbols in the table are as follows:
• SM: Master station sequence scan time
• LS: Link scan time
• SL: Local station sequence scan time
• n: LS  SM (Digits past the decimal point are rounded up to the nearest integer.)
• t: LS  m  SM (Digits past the decimal point are rounded up to the nearest integer.)
• k: LS  SL (Digits past the decimal point are rounded up to the nearest integer.)
• m: Constant set in the extended cyclic setting
Expanded cyclic setting
With block guarantee of cyclic data per station
Calculation
value
Asynchronous mode
(SM  n) + [LS  {(1  m) + 1}] + {SL
Normal value
 (k + 1)}
(SM  n) + [LS  {(2  m) + 1}] + {SL
Max. value
 (k + 1)}
(b) Calculation example
Master station sequence scan time of 20ms, link scan time of 3ms, expanded cyclic setting "double", and local
station sequence scan time of 10ms
With block guarantee of cyclic data per station
Calculation
value
Asynchronous mode
(20  1) + [3  {(1  3) + 1}] + {10 
Normal value
(1 + 1)} = 52ms
(20  1) + [3  {(2  3) + 1}] + {10 
Max. value
(1 + 1)} = 61ms
Transmission delay time of master station <-> local
station (Ver.2 compatible device station)
Single
m
Synchronous mode
{(SM  t)  2} + {SL  (k + 1)}
{(SM  t)  3} + {SL  (k + 1)}
Synchronous mode
{(20  1)  2} + {10  (1 + 1)} = 60ms
{(20  1)  3} + {10  (1 + 1)} = 80ms
Double
1 3
Without block guarantee of cyclic data per station
Asynchronous mode
SM + [LS  {(1  m) + 1}] + SL
SM + [LS  {(2  m) + 1}] + SL
Without block guarantee of cyclic data per station
Asynchronous mode
20 + [3  {(1  3) + 1}] + 10 =
42ms
20 + [3  {(2  3) + 1}] + 10 =
51ms
APPENDICES
Quadruple Octuple
7 15
Synchronous mode
(SM  t)  2
(SM  t)  3
Synchronous mode
(20  1)  2 = 40ms
(20  1)  3 = 60ms
443
A