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(4) Data flows in synchronous and asynchronous modes
The data flows in both the synchronous and asynchronous modes are explained using examples of
communications between the master station and remote I/O stations.
Even if latched device (listed in "CPU side device" in the table below) data are cleared to 0 by a program at reset of the CPU
module or at power off and on, the latched data may be output depending on the timing of link scan and link refresh.
For how to prevent output of latched device data, perform "Method for disabling output" listed in the table below.
CPU side device
Latch relay (L)
File register (R, ZR)
Extended data register (D)
Extended link register (W)
Device in the latch range
(a) Data flow in the asynchronous mode
Programmable controller CPU
(Sequence scan)
Master station buffer memory
(Remote input RX)
Link scan
Response time of the first station
Response time of the corresponding station
Response time of the final station
Responses from remote
I/O stations
I: Delay time due to response delay of remote I/O station
II: Delay time of transmission from the remote I/O station to the master station
III: Delay time from reception by the master station to storage in the buffer memory
IV: Delay time until the master station's information is refreshed in the programmable controller CPU
Clear the value of the device to 0 using the initial device
value.
For how to set an initial device value, refer to the MELSEC-L
CPU Module User's Manual (Function Explanation, Program
Fundamentals).
Delete all latch range settings.
Input 1)
Input 2)
Input 3)
I
II
III
Transmission
delay time
CHAPTER 8 FUNCTIONS
Method for disabling output
IV
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